Staff PDK Engineer – LVS / PERC Development

Job Details:

Job Description:

Join Intel to be at the forefront of technology innovation as we shape the future of semiconductor design and enable the Angstrom era of compute and AI. As a Process Design Kit (PDK) Engineer within the Design Technology Platform team at Intel Foundry, you will play a pivotal role in delivering best-in-class PDKs that empower Intel's product design teams to model, implement, and verify their designs before manufacturing. This role uniquely positions you to drive innovation, collaborate with industry-leading experts and EDA partners, and ensure the highest quality standards for Intel's Process Design Kits. Through your work, you will contribute directly to Intel's success, enabling groundbreaking products that enrich lives worldwide.

In this role you will be the experienced technical contributor in developing advanced PDK Electrical Rule Checks in LVS and ESD protection verification solution on Intel's process technologies, including but not limited to:

• Complete breadth coverage across multiple EDA LVS/PERC verification platforms (Cadence Pegasus, Siemens Calibre and Synopsys ICV).
• Continuous advancement of holistic electrical rule verification methodology and solution.

Candidate will work with technology specification owners and validation teams in a coordinated fashion to ensure a high-quality solution. Interaction with Process Development Teams, and EDA vendors is expected on a frequent basis in enabling production quality verification solutions.

Extended Responsibilities:

• Drive the adoption of industry-standard methods and facilitate ease of use for internal and external design communities.
• Develop and implement QA and regression solutions to qualified the PDK collaterals.
• Conduct root cause analyses for design issues related to process technology, innovation to enhance design methodologies and tool efficiency.
• Mentoring junior team to develop team competency.

#designenablement

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must possess a BS degree with 7+ years of experience or MS degree with 5+ years of experience or PhD degree with 3+ years of experience in Electronics Engineering, Electrical Engineering and Computer Engineering or related field.

3+ years of experience in one the following:

• DRC/LVS runset development in Calibre-SVRF, ICV-PXL, or Pegasus language.
• EDA PERC (Programmable Electrical Rules Check) rule deck development.
• ESD protection verification solution development in PERC or Static ESD verification.
• Scripting in Python, PERL or TCL.

Preferred Qualifications:

• 3+ years of experience developing PDKs for advanced process technologies.
• Familiarity with IC physical design, layout, and verification flows.
• Knowledge of IC manufacturing process flows.
• Exposure to DA/CAD/CAE environments involving circuit simulation, physical verification, parasitic extraction, P2P resistance, current density analysis and/or net listing tools.
• Strong problem-solving skills and the ability to drive improvements across tools and methodologies.

Take the next step in shaping Intel's future by applying your expertise and leadership to drive innovation, inspire a high-performing team, and deliver impactful solutions that redefine the industry.

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.