Staff Design for Test STA Engineer

Austin, Texas, United States; Santa Clara, California, United States Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

As a Staff Design for Test STA Engineer at Tenstorrent, you will be a key technical leader in ensuring the testability, quality, and performance of our next-generation AI processors. This role requires a good understanding of both Design for Test (DFT) architecture and implementation, as well as comprehensive expertise in Static Timing Analysis (STA) for complex SoCs. You will be responsible for defining and implementing the full DFT methodology for our high-speed, multi-core designs, owning the top-level timing constraints and sign-off for all DFT modes, and collaborating closely with RTL, Physical Design, and Product Engineering teams to achieve first-pass silicon success.

This role is hybrid, based out of Santa Clara, CA or Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

Deep knowledge of core DFT concepts including Scan Compression and insertion, Memory BIST and repair schemes, JTAG/IJTAG, and at-speed test methodologies.
Comprehensive understanding of Clock Domain Crossings (CDC), Reset Domain Crossings (RDC), timing sign-off modes and constraints, and proficiency in using industry-leading Static Timing Analysis tools (e.g., Synopsys PrimeTime, Cadence Tempus etc).
Deep knowledge of DFT specific timing modes including JTAG, Scan Shift, Scan Slow Capture, Scan Fast Capture, Memory BIST etc.
Experience in Verilog/SystemVerilog RTL coding and back-annotated gate-level verification.

What We Need

Coordinate DFT requirements across SOC, IP and product teams and work closely with multi-functional teams to support DFT RTL level insertion, synthesis and scan insertion, place-and-route, and static-timing-analysis and timing closure.
Lead the definition, generation, and validation of comprehensive DFT timing constraints (SDC) to ensure timing closure for all test modes (e.g., Scan, JTAG, Memory BIST).
Own the STA sign-off for DFT modes at both the block and top-level, including corners and operating conditions, using industry-standard tools (e.g., PrimeTime, Tempus etc).
Work closely with the Physical Design team (Synthesis, P&R) to drive timing convergence, resolve complex timing violations, and generate necessary timing ECOs.
Identify and implement improvements to existing DFT and STA flows, enhancing efficiency and robustness.
Participate in ATE targeted test patterns, validation and silicon- debug
Work closely with test and product engineering teams on silicon characterization and validation.

What You Will Learn

Advanced Design for Test (DFT) methodologies for cutting-edge AI processor architectures, including comprehensive scan insertion, Memory BIST, and at-speed test strategies
In-depth Static Timing Analysis (STA) techniques for complex multi-core SoCs, mastering industry-standard tools like PrimeTime and Tempus to ensure timing closure across diverse operational modes
Sophisticated cross-functional collaboration skills, working seamlessly with RTL, Physical Design, and Product Engineering teams to drive first-pass silicon success
Innovative problem-solving approaches for resolving complex timing violations and optimizing test flows in high-performance semiconductor design environments

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

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Staff Design for Test STA Engineer

This role is hybrid, based out of Santa Clara, CA or Austin, TX.

Who You Are

Deep knowledge of core DFT concepts including Scan Compression and insertion, Memory BIST and repair schemes, JTAG/IJTAG, and at-speed test methodologies.

Comprehensive understanding of Clock Domain Crossings (CDC), Reset Domain Crossings (RDC), timing sign-off modes and constraints, and proficiency in using industry-leading Static Timing Analysis tools (e.g., Synopsys PrimeTime, Cadence Tempus etc).

Deep knowledge of DFT specific timing modes including JTAG, Scan Shift, Scan Slow Capture, Scan Fast Capture, Memory BIST etc.

Experience in Verilog/SystemVerilog RTL coding and back-annotated gate-level verification.

What We Need

Coordinate DFT requirements across SOC, IP and product teams and work closely with multi-functional teams to support DFT RTL level insertion, synthesis and scan insertion, place-and-route, and static-timing-analysis and timing closure.

Lead the definition, generation, and validation of comprehensive DFT timing constraints (SDC) to ensure timing closure for all test modes (e.g., Scan, JTAG, Memory BIST).

Own the STA sign-off for DFT modes at both the block and top-level, including corners and operating conditions, using industry-standard tools (e.g., PrimeTime, Tempus etc).

Work closely with the Physical Design team (Synthesis, P&R) to drive timing convergence, resolve complex timing violations, and generate necessary timing ECOs.

Identify and implement improvements to existing DFT and STA flows, enhancing efficiency and robustness.

Participate in ATE targeted test patterns, validation and silicon- debug

Work closely with test and product engineering teams on silicon characterization and validation.

What You Will Learn

Advanced Design for Test (DFT) methodologies for cutting-edge AI processor architectures, including comprehensive scan insertion, Memory BIST, and at-speed test strategies

In-depth Static Timing Analysis (STA) techniques for complex multi-core SoCs, mastering industry-standard tools like PrimeTime and Tempus to ensure timing closure across diverse operational modes

Sophisticated cross-functional collaboration skills, working seamlessly with RTL, Physical Design, and Product Engineering teams to drive first-pass silicon success

Innovative problem-solving approaches for resolving complex timing violations and optimizing test flows in high-performance semiconductor design environments

Apply for this job

indicates a required field