Intel은 반도체 설계의 STA(Static Timing Analysis)를 수행할 인턴을 모집합니다. 전기/전자/컴퓨터 공학 전공 3~4학년 학생을 대상으로 하며, 디지털 로직 및 Verilog/SystemVerilog에 대한 이해가 필수입니다. 주 4회 현장 근무가 가능하고 6개월 이상 인턴십을 수행할 수 있어야 합니다.
An STA (Static Timing Analysis) Design Intern is responsible for evaluating the timing margins of semiconductor logic designs (ASIC/SoC) to ensure the chip will function at target speeds without errors. Key tasks include running timing constraints, analyzing slack, and fixing setup/hold violations.
Perform Static Timing Analysis (STA): relating tasks such as kicking off runs, perform timing analysis and timing fixes.
Constraint management: Assist senior engineers in creating, updating and debugging timing exceptions.
Scripting: Write scripts to enhance/speed up the process of the current available flows.
Third-year or Final-year student currently pursuing a Bachelor's degree in Electrical Engineering, Computer Engineering, or VLSI Systems or a closely related field (Physics, Maths).
Be able to work onsite for 4 days per week.
Be able to commit to at least a 6-month internship program.
Strong verbal and written communication skills in English.
Knowledge Base: Strong foundational grasp of digital logic, flip-flops, clock domains, and CMOS circuit design.
Tools: Familiarity with Linux environments and basic exposure to EDA tools.
Programming: Proficient in scripting languages (Tcl, Python, or Perl) and hardware description languages (Verilog or SystemVerilog).
Soft Skills: Strong analytical and problem-solving skills, paired with a collaborative team spirit and a passion for continuous learning.
Attractive internship allowance
Training programs, opportunities to be involved in multinational projects.
Exciting extracurricular and sports programs for employees
Well-invested facilities, putting safety first.
Shuttle bus system at many places in Ho Chi Minh City, Binh Duong, Dong Nai.
High-quality cafeteria, lunch allowance.
Safe, stable and dynamic working environment.
Student / Intern
Shift 1 (Vietnam)
Vietnam, Ho_Chi_Minh_City
Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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