Intel에서 ASIC 검증 전략을 수립하고 UVM 기반의 고도화된 검증 환경을 구축할 시니어 엔지니어를 채용합니다. 5년 이상의 ASIC/FPGA 검증 경력과 SystemVerilog 활용 능력이 필수입니다. 차세대 반도체 개발을 주도하며 기술 리더십을 발휘하고 주니어 팀원을 멘토링하는 핵심 역할을 수행하게 됩니다. 원격 근무가 가능한 환경에서 최신 검증 방법론을 적용할 기회입니다.
Intel is seeking a highly qualified candidate to join our ASIC design verification team in a dynamic and forward-thinking organization focused on next-generation semiconductor product development. Our team focuses on being nimble, adaptable, lean and efficient to drive cutting-edge, customer impacting technology development. We embrace innovative and efficient methodologies that drive at-scale product execution.
Advance your career with cutting-edge verification techniques including coverage-driven verification, formal methods, and performance analysis. Lead custom SystemVerilog/UVM development, master industry-standard EDA tools, architect verification strategies for complex ASICs, and mentor emerging talent while independently driving verification closure. Join our fast-paced semiconductor team where your technical leadership shapes next-generation chip development through comprehensive methodologies and innovative verification solutions. Transform challenging projects into career-defining achievements.
If you are passionate about building products faster and more efficiently than anyone else on the planet, we want you on our team.
Key Responsibilities:
Define Project Specific Verification Strategy: Defines and implement scalable and reusable verification plans, test benches, and the verification environments for blocks, subsystems, and SoCs. Ensure meeting the required coverage levels and conform to microarchitecture specifications.
Lead Verification Execution: Create detailed test plans and drives technical reviews with design and architecture teams to validate these plans and proofs.
Executes verification plan: Implement and run block/subsystem/cluster/soc simulation models to verify the design, analyze power and performance, and identify bugs.
Investigate and Resolve Bugs: Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests.
Collaborate Across Teams: Work closely with SoC architects, micro architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
Enhance Future Verification Methodologies: Continuously improves existing functional verification infrastructure and methodologies.
Absorbs learnings: From post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages and proliferates to future products.
Lead and mentor others: inspire and guide junior engineers, fostering their growth and development. Your expertise will be instrumental in cultivating a collaborative and innovative environment where every team member thrives.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Bachelor's degree in electrical engineering, computer engineering, computer science, or in other relevant STEM related degree.
5+ years of experience in ASIC/FPGA design verification
Experience in developing UVM and/or Formal based verification architectures and methodologies.
Experience with industry standard protocols such as AMBA AXI/AXI-S/CHI/APB and Low-speed communication protocols such as UART, SPI or I2C/I3C
Hands-on experience with simulators (Synopsys VCS, Cadence Xcelium, or equivalent).
Experience with coverage-driven verification, constrained-random testing and strong debugging skills.
Experience with scripting languages such as Python, TCL, and Shell scripting.
Preferred Qualifications:
Graduate/post-graduate degree in electrical engineering, computer engineering, computer science, or any STEM related degree with overall 8+ yrs. of experience.
Skilled in various validation concepts and debug techniques relevant to ASIC/FPGA domain.
Collaborative, able to communicate well with counterparts and stakeholders.
Strong written and verbal communication skills.
Strong analytical ability and problem-solving skills.
Experience in defining testbench architecture, constrained random verification methodologies.
Experience in processor-based verification using C/C++ with UVM-based verification environments.
Define and execute validation of IPs and/or SOC from spec to tape-in including setting verification strategy, creating test bench and components, defining test plan, writing tests, debugging, coverage and analysis.
Low power experience (e.g., UPF).
Experience in CXS stream, DDR, PCIe and/or Ethernet, UCIe protocols.
Experience in EDA tools and reusable testbench for subsystem and SoC that deploys 3rd party VIPs.
Experience with formal verification techniques and tools is an asset.
Experienced Hire
Shift 1 (Canada)
Virtual Canada
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
N/A
Annual Salary Range for jobs which could be performed in Canada
CAD 153,910.00-217,280.00
This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.
Intel is committed to a culture of accessibility. Intel provides accommodations to applicants and employees with disabilities. Find information and request accommodation here.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
