Senior Testchip SoC Physical Design Engineer (Integration & Methodology)
하드웨어 엔지니어정규직시니어 · 5년 이상
Intel에서 차세대 반도체 공정 검증을 위한 Testchip SoC 물리적 설계 및 통합 방법론을 담당할 Senior 엔지니어를 채용합니다. Physical Design 및 Layout 설계 경험이 필수이며, Cadence Virtuoso 또는 Synopsys 도구 활용 능력이 요구됩니다. 최첨단 공정 노드에서 설계부터 테이프인까지 전 과정을 주도하게 됩니다.
Join the Design Technology Platform (DTP) organization within Intel Foundry as part of the X-Chip SoC Full-Chip Integration team. This team plays a critical role in enabling next-generation semiconductor innovation by delivering testchip platforms that validate advanced process technologies and support high-volume manufacturing readiness.
In this role, you will contribute to the development of physical design methodologies and drive full-chip SoC integration for cutting-edge testchip vehicles. You will collaborate across design, process, and manufacturing teams to ensure high-quality, scalable solutions for advanced technology nodes.
See Intel Benefits for more details.
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications and Experience:
Master's degree in electrical engineering or related field with minimum of 5 years of experience in the following areas:
Preferred Qualifications and Experience:
Experience in Definition of Testchip/Product design from Concept to Execution Commit
Experience in working with Foundry teams on negotiating features to exercise in design
Proven Project Management skills on coordinating and tracking the entire design cycle of a project from Feature definition to final Tape-in
Previous related work experience in a semiconductor foundry preferred
Experienced Hire
Shift 1 (United States of America)
US, Oregon, Hillsboro
US, California, Santa Clara, US, Texas, Austin
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.