인텔의 Senior SoC Network Subsystem Architect는 차세대 IPU/DPU 플랫폼을 위한 고성능 네트워크 서브시스템 아키텍처를 설계하고 주도합니다. 7년 이상의 관련 경력과 네트워킹 ASIC/SoC 아키텍처에 대한 깊은 전문 지식이 필수입니다. 데이터 센터 및 AI 워크로드를 위한 패킷 처리 파이프라인과 QoS 프레임워크를 정의하며, 하드웨어 및 소프트웨어 팀과 협력하여 기술적 방향성을 이끌어갈 전문가를 찾습니다.
The CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon. Our team architects next-generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems.
We are seeking a Senior SoC Network Subsystem Architect to define and lead the architecture of high-performance network subsystems for next-generation IPU/DPU platforms. This role focuses on designing scalable, programmable networking pipelines that support hyperscale and cloud data center workloads.
You will drive the end-to-end Network Subsystem (NSS) architecture, including packet processing pipelines, protocol engines, QoS frameworks, and observability features. This is a highly cross-functional leadership role requiring deep technical expertise and strong collaboration across hardware, software, and systems teams.
1. Own end-to-end NSS architecture, including packet processing pipelines, protocol engines, and interface datapaths
2. Architect high-performance packet pipelines supporting hundreds of millions of packets/sec throughput and processing flows
3. Drive architectural direction for programmable vs. fixed-function pipeline balance and future extensibility
4. Specify network subsystem pipeline scaling strategies and define multi-generation NSS architecture roadmap
6. Lead design decisions for pipeline partitioning, feature scalability, and backward compatibility
1. Architect advanced scheduling frameworks (per-flow shaping, multi-level scheduling, traffic class isolation)
2. Define QoS models to support multi-tenant workloads, virtualization, and service chaining
1. Define architecture for telemetry, performance counters, and real-time observability of pipeline behavior
2. Architecture support for field debug, failure triage, and large-scale deployment monitoring
1. Collaborate across SoC, compute, memory, SW/FW, validation, and customer teams to drive architecture closure
2. Interface with external customers to translate workload requirements into NSS architecture decisions
3. Lead architectural reviews and influence cross-team technical direction
Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life.
See Intel Benefits for more details.
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Intel U.S. Immigration Sponsorship Information
Minimum Qualifications and Experience:
Bachelor’s degree in Electrical/Computer Engineering, Computer Science or related degree with 7 + years of experience.
You must have 7+ years of experience in the following:
Preferred Qualifications and Experience:
Experienced Hire
Shift 1 (United States of America)
US, California, Santa Clara
US, Arizona, Phoenix, US, California, Folsom, US, California, San Jose, US, Oregon, Hillsboro, US, Texas, Austin
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
N/A
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
