인텔 페낭에서 Senior Logic Design Verification Engineer를 채용합니다. UVM 및 SystemVerilog를 활용한 15년 이상의 설계 검증 경력이 필수입니다. 전력 관리 컨트롤러 IP의 검증 환경 구축과 RTL 디버깅을 주도하며, 하이브리드 근무 환경에서 글로벌 팀과 협업하게 됩니다. 반도체 설계 분야의 전문성을 발휘할 숙련된 엔지니어를 찾습니다.
The world is transforming - and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We're inviting dynamic and imaginative technocrats to take part in creating it. The Power Management Controller IP (PMC) is responsible for managing the system boot and power for client and server chipsets. As a member of the PMC Logic Design Verification team: • You will work closely with IP architects to define and develop verification testbench and building RTL models for verification • You will be validating and verifying the functionality of new architectural features of next generation designs by developing testplan, tests content or test tools • You will be finding and implementing corrective measures for failing RTL tests, analyzes and uses results to modify testing • Your influence will cross-organizational boundaries with our manufacturing and validation partners • Your expertise will grow as you debug and resolve issues on system platforms using software and RTL simulation tools
Qualifications • Possess a Bachelor's, a Master's degree or a Ph.D. in Electronics Engineering, Computer Engineering, or equivalent with relevant experience in IP/SoC design or verification development • At least 15 years of relevant working experience in design verification with UVM and System Verilog • Familiarize with UVM Verification Components and Bus-functional Models (BFM) and building Testbench from ground up • Strong in UVM application eg UVM Virtual Sequencer, Factory and Formal Property will be advantage • Communicates well with good influencing skills • Strong in analysis, debugging skills, and creative in problem solving • Motivated, Self-driven and Independent Relevant Qualifications: • Working in Assembly language, embedded firmware, real-time operating system RTOS, BIOS, and HW/SW interactions. Working experience with ACPI spec, power management. • Hardware-Firmware co-validation development and debugging environments. • Familiar with Linux, industry scripting languages (Python, Perl), and simulation tools. • Behavioral traits including, but not limited to, strong written and verbal communication skills, tolerance of ambiguity, problem solving, teamwork, attention to detail, commitment to task, quality focus and Knowledge of Agile.
Experienced Hire
Shift 1 (Malaysia)
Malaysia, Penang
Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
N/A
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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