Principal CPU Microarchitect - RISC-V & AI Compute

Principal CPU Microarchitect - RISC-V & AI Compute

Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Our Tensix Team is building the future of AI compute with a ground-up architecture centered on scalable RISC-V processors. As we push performance boundaries, we’re reimagining the frontend of our RISC-V cores to deliver major gains in programmability, efficiency, and developer experience. This is a rare opportunity to shape the CPU architecture at the heart of our AI platform and lead one of the most strategic technical efforts at Tenstorrent.

This role is hybrid, based out of Toronto, ON, Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Experienced Microarchitect: 10+ years of deep expertise in CPU performance modeling and microarchitecture design.
• AI Workload Expert: Deeply familiar with the computational and memory bottlenecks of modern AI workloads, particularly Large Language Models (LLMs).
• Hardware-Software Co-Designer: Driven to architect custom instruction set extensions and validate their performance gains against real-world workloads.
• Ways to stand-out: Familiarity with open-source RISC-V cores, AI-based agentic workflow experience

What We Need

• Profile & Analyze: Dissect cutting-edge AI workloads to identify execution bottlenecks and translate those insights into definitive CPU performance requirements.
• Architect High-Performance Cores: Drive the microarchitecture of custom RISC-V CPU cores, balancing aggressive Performance, Power, and Area (PPA) targets.
• Innovate the ISA: Design and implement custom instructions that unlock massive performance gains without sacrificing compiler programmability or developer velocity.
• Cross-Functional Collaboration: Partner tightly across compiler, software, and hardware teams to co-design Tenstorrent’s next-generation AI compute architecture.

What You Will Learn

• How modern AI models stress CPU architecture and influence design decisions.
• The interplay between compiler design, CPU microarchitecture, and real-world performance.
• How Tenstorrent’s unified hardware-software stack enables breakthrough performance for general-purpose AI compute.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.  Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).   These requirements apply to persons located in the U.S. and all countries outside the U.S.  As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.  If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

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