Principal Analog Circuit Design Engineer - SerDes
연 CA$214,452~CA$302,753하드웨어 엔지니어정규직리드 · 8년 이상
고속 SerDes 회로의 설계 및 검증을 주도하며, 레이아웃 및 주니어 엔지니어에게 기술적 방향성을 제시하고 멘토링을 수행해요. 전기전자공학 석사 학위와 8년 이상의 아날로그/혼합 신호 설계 경력이 필수이며, 7nm 이하 FinFET CMOS 공정 경험이 필요해요. 현재는 원격 근무 중이나, 향후 토론토 사무실이 운영되면 주 4일 이상 출근하는 하이브리드 근무로 전환될 예정이에요. PCIe 및 이더넷 표준에 대한 이해가 요구되며, 실리콘 검증 및 디버깅 업무를 직접 수행해야 해요.
We are seeking a highly experienced and motivated Principal Analog Design Engineer to lead the design and validation of cutting-edge analog circuits for high-speed (112G and 224G) SerDes applications. In this role, you will be a key technical driver in the definition, execution, and validation of complex analog and mixed-signal designs.The ideal candidate is self-driven, detail-oriented, and thrives in a fast-paced environment. You will actively participate in technical discussions across multiple disciplines, including analog/mixed-signal design, post-silicon validation, and system-level collaboration.
This role involves providing technical direction and mentorship to layout and less experienced analog design engineers, fostering a collaborative and knowledge-sharing culture. You will engage closely with cross-functional teams, including systems, digital design, and test engineering, to ensure robust design implementation and validation.
Strong problem-solving skills, analytical thinking, and a commitment to execution excellence are essential. As a principal-level engineer, you will be expected to demonstrate a proven track record of delivering high-quality results in advanced FinFET CMOS technology within high-speed SerDes design environments. Excellent documentation and presentation skills are also required to clearly communicate complex design concepts and results.
SPECIAL NOTE - Intel is in the process of securing office space in the greater metropolitan area of Toronto, Ontario. This office will serve as your assigned work location in the future. Once the site is operational, your position will follow Intel’s hybrid work model, which currently requires on-site presence at least four days per week. Until the office is ready, you will be classified as a remote employee and will be working virtually from the greater metropolitan area of Toronto, Ontario.
Minimum Qualifications
Master's degree in Electrical Engineering, Electronics Engineering, or related field.
8+ years of experience in analog/mixed-signal circuit design for high-speed SerDes applications.
Proven expertise in one or more of the following areas: PLL, CDR, CTLE, DFE, ADC, or Transmitter (TX) design.
Strong understanding of high-speed communication standards such as PCIe (Gen5/Gen6) and Ethernet (100G/400G/800G).
Solid foundational knowledge of analog design principles-noise, jitter, matching, stability, and linearity.
Hands-on experience with advanced FinFET CMOS process technologies (7nm or below).
Proficiency in analog design and simulation tools such as Cadence Virtuoso/ADE, HSPICE, or equivalent.
Experience in silicon bring-up, post-silicon validation, and lab debug of analog circuits.
Excellent communication, documentation, and presentation skills.
Strong problem-solving attitude and ability to deliver under tight schedules in a collaborative environment.
Preferred Qualifications
Ph.D. in Electrical Engineering, Electronics Engineering, or related field.
10+ years of experience in analog design for high-speed SerDes (56G/112G/224G) applications.
Deep expertise in transmitter and receiver architecture, CDR loops, equalization techniques, and advanced ADC architectures.
Familiarity with next-generation standards such as PCIe 6.0+, 800G/1.6T Ethernet, JESD, and other SerDes protocols.
Hands-on experience in behavioral modeling (Verilog-A), MATLAB-based analysis, and automation scripting (Python/Tcl/Perl).
Strong understanding of signal integrity, channel modeling, and system-level link performance.
Proven ability to mentor junior engineers, guide layout implementation, and drive design reviews.
Demonstrated leadership in cross-functional technical discussions and decision-making.
Team player with a collaborative mindset, willingness to share knowledge, and a hands-on approach to problem-solving.
Experienced Hire
Shift 1 (Canada)
Virtual Canada
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
Annual Salary Range for jobs which could be performed in Canada CAD 214,452.00-302,753.00
This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.
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