Intel Foundry에서 Physical Verification Engineer를 채용합니다. 고급 CMOS 공정(22nm 이하) 환경에서 고객의 레이아웃 검증 및 기생 추출 문제를 해결하는 핵심 역할을 수행합니다. 미국 시민권자로서 보안 인가 취득이 가능해야 하며, 관련 분야 3년 이상의 경력이 필수입니다. 반도체 설계 검증 분야의 전문성을 발휘하여 국가 안보 및 첨단 파운드리 기술 발전에 기여할 인재를 찾습니다.
Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.
The Aerospace, Defense & Government (ADG) Senior Physical Verification Application Engineer provides specialized technical support to Intel Foundry Services customers on layout verification and parasitic extraction. This critical role ensures successful customer tape-outs by resolving complex physical design challenges, driving quality improvements in design kits, and delivering comprehensive technical guidance on advanced verification methodologies.
Provide comprehensive technical support to Intel Foundry Services customers on layout verification and parasitic extraction challenges
Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors on physical and layout design rules and extraction issue resolution
Resolve complex verification challenges across advanced CMOS processes and ensure successful customer design implementations
Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams
Drive quality improvements in design kits and documentation to remove barriers to successful customer design tape-outs
Develop best practice guidelines for physical verification flows and methodologies across advanced process technologies
Lead optimization of physical verification flows for advanced CMOS processes (22nm and below)
Provide technical direction on layout verification methodologies including DRC, LVS, ERC, and PERC implementations
Drive methodology improvements to streamline customer design workflows and enhance verification productivity
Deliver customer-facing technical support with focus on physical verification challenges and solutions
Support customers through complex verification issues and advanced process technology adoption
Ensure maximum customer satisfaction through expert guidance and responsive technical support
Self-driven and results-oriented with capability to effectively manage multiple complex tasks
Strong analytical problem-solving skills for complex physical verification challenges
Effective communication skills with experience in collaboration, active listening, and providing constructive feedback
The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
US Citizenship required
Ability to obtain a US Government Security Clearance
Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study
3+ years of experience with advanced CMOS processes (22nm and below)
3+ years of combined experience in layout verification and parasitic extraction EDA tools
3+ years of experience in one or more of the following scripting languages (Python, Perl, Tcl, and/or shell scripting.)
Active US Government Security Clearance with a minimum of Secret level
Post Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study
Hands-on experience in one or more areas ( LVS, DRC,ERC, PERC)
Experience in parasitic extraction tools i.e. StarRC, Quantus, or xACT EDA tools
Experience with major layout editing EDA tools and flows such as ICV, Calibre and Pegasus EDA tools
Rule deck coding experience in ICV, Calibre or Pegasus EDA tools
Experience in providing technical direction to engineering teams, including but not limited to customer support, driving methodologies to streamline design work
Customer facing experience
Opportunity to work with cutting-edge physical verification technologies for aerospace, defense, and government applications
Direct customer engagement and technical leadership in advanced semiconductor verification
Access to Intel's most advanced foundry technologies and comprehensive verification tool suites
Competitive compensation
Professional development in physical verification methodologies and foundry services
Direct impact on national security through advanced semiconductor verification solutions
Experienced Hire
Shift 1 (United States of America)
US, Arizona, Phoenix
US, California, Santa Clara, US, Oregon, Hillsboro
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $128,880.00-245,160.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
