혼합 신호 및 고속 IP를 위한 논리 설계와 RTL 코딩, 시뮬레이션을 수행해요. 아키텍처 및 마이크로아키텍처 정의에 참여하며, 아날로그 동작 모델링과 회로 시뮬레이션을 통해 설계를 최적화해요. 검증 계획을 검토하고 실패한 RTL 테스트에 대한 수정 조치를 이행해요. SoC 고객을 지원하여 IP 블록의 고품질 통합을 보장하는 업무를 담당해요.
Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal and/or high-speed IPs required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods for mixed signal designs including analog behavior modeling and circuit simulation to write RTL and optimize mixed signal logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high-quality integration of the IP block.
Shift 1 (Malaysia)
Malaysia, Penang
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
N/A
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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