Intel은 DDR PHY IP 검증을 담당할 Mixed Signal IP Verification Engineer를 채용합니다. System Verilog, UVM을 활용한 검증 흐름 전반에 대한 경험이 필수입니다. 테스트 벤치 설계, 디버깅 및 RTL 개발팀과의 협업을 수행합니다. 5~10년의 경력을 보유한 전문가를 찾고 있으며, DDRPHY 및 DFx 경험자를 우대합니다.
The Memory PHY Group (MPG) within the Central Engineering Group (CEG) is looking for a Pre-Silicon Verification Engineer to deliver latest and best-in-class DDR PHY IP for SoCs across Intel for the latest desktop, laptop, and other products. In this role you will perform all aspects of the functional verification flow to ensure design will meet specification requirements. You will perform IP Verification related tasks such as creating test plan, defining TB architecture and creating test benches, validating design and micro-architectural implementation. You will be automating validation tasks to drive efficiency. You will be analyzing results and help to debug issues in pre-silicon environment at IP, subsystem and SOC level. You will collaborate with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals. The additional responsibilities include: development of validation strategies and plans, scoping and driving execution for different area of pre-Si validation, driving technical reviews of plans and proofs with design and architecture teams, maintaining and improving existing functional verification infrastructure and methodology, providing guidance and help to team members in understanding issues, removing roadblocks and ensuring issue resolution through strong demonstration of Intel Cultural values.
Minimum Qualifications: • Candidate must possess a BS, MS degree with 5-10 years of relevant industry experience in Design verification, System Verilog and OVM/UVM. • Candidate must be experienced in validation flow right from testbench architecture and test plan creation to verification closure, waveform debug, functional coverage, code coverage, VCS NLP and non-NLP simulations and GLS • Capable of multitasking in dynamic environment with multiple teams from different geos • Solid verbal and written communication skills • Excellent debug and problem solving skills Preferred Qualifications: • Knowledge of DDRPHY validation with good hold on DFx features • Good scripting skills in Python/Perl • Exposed to Git version control VSCode GitHub CoPilot or any other AI experience
Experienced Hire
Shift 1 (India)
India, Bangalore
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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