Mixed Signal Design Verification Engineer

Job Details:

Job Description:

Performs functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to mixed signal microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology.

Qualifications:

Minimum Qualifications

• Candidate must possess Bachelor's or Master's degree in Electronics, VLSI Engineering, or a related field with 4-10 years of relevant industry experience and good proficiency in verification of mixed signal IP Design.
• Candidate must be experienced in validation flow right from testbench architecture and test plan creation to verification closure, waveform debugs, functional coverage, code coverage, VCS NLP and non-NLP simulations and GLS.
• Strong knowledge of SystemVerilog and UVM methodology, experience in functional and coverage driven verification.
• Expertise in constraint-random test generation, failure root cause analysis and debugging of complex mixed signal designs.
• Capable of multitasking in dynamic environment with multiple teams from different geos.
• Solid verbal and written communication skills.
• Excellent debug and problem solving skills.

Preferred Qualifications

• Knowledge of UCIe PHY validation or any high speed PHY IO Mixed Signal IP validation.
• Knowledge of Formal Property Verification tools, exposure to emulation.
• Good scripting skills in Python/Perl.
• Exposed to Git version control.
• VS Code GitHub CoPilot or any other AI experience.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.