인텔에서 Mixed Signal Design Verification Engineer를 채용합니다. SystemVerilog, UVM을 활용한 혼합 신호 로직 검증 및 테스트 벤치 구축을 담당합니다. DDR 프로토콜 지식과 ASIC/SoC 검증 경력이 필수입니다. 하이브리드 근무가 가능하며, 최첨단 IP 검증을 통해 인텔의 컴퓨팅 솔루션을 주도할 인재를 찾습니다.
The Role and Impact As a Mixed Signal Design Verification Engineer, you will play a pivotal role in verifying and enhancing the functionality of mixed signal logic components, ensuring Intel's products meet the highest standards of quality, performance, and innovation. In this role, you will collaborate with cross-functional teams to validate cutting-edge IPs, pushing the boundaries of technology and innovation. Your work will directly contribute to Intel's leadership in delivering best-in-class solutions that power the future of computing. Key Responsibilities - Perform functional verification of mixed signal logic components, including analog behavioral modeling, to ensure compliance with design specifications. - Develop comprehensive IP verification plans, test benches, and verification environments to achieve thorough coverage of mixed signal microarchitecture specifications. - Define and execute verification plans, including running system simulation models, analyzing power and timing, and identifying and resolving design bugs. - Debug failing tests in the presilicon environment through root cause analysis and implement corrective measures to ensure design functionality. - Collaborate closely with digital and analog architects, RTL developers, and physical design teams to improve architectural and microarchitectural features. - Lead technical reviews of test plans and validation proofs with design and architecture teams while documenting findings and ensuring thorough validation coverage. - Maintain, refine, and enhance functional verification methodologies, infrastructure, and tools to keep pace with industry advancements.
Minimum Qualifications - Bachelor's or Master's degree in Electronics, VLSI Engineering, or a related field. - 4-12 years of experience with a Bachelor's degree, or 3-10 years of experience with a Master's degree in ASIC or SoC verification. - Excellent knowledge on DDR4/DDR5/LP5/LP6 protocol - Expertise in System Verilog, UVM, and Verilog for mixed signal verification. - Hands-on experience with industry-standard EDA tools such as Synopsys VCS, Cadence Xcelium/JasperGold, or Mentor Questa. - Strong scripting skills in Python, Perl, or Tcl for testbench automation and process efficiency. - In-depth knowledge of standard protocols including JTAG, IJTAG, CRI, and APB, as well as multi-clock domain mixed signal designs. - Proficiency in constraint-random test generation, root cause analysis, and debugging of complex mixed signal designs. Preferred Qualifications - Experience with low-power design techniques, including UPF and clock gating, to optimize power consumption. - Familiarity with Formal Property Verification tools and version control systems such as Git or Perforce. - Strong collaboration and communication skills, with the ability to thrive in a dynamic, multidisciplinary team environment. Join us to drive verification excellence and shape the future of technology at Intel. Apply today to become part of our mission to deliver transformative innovations.
Experienced Hire
Shift 1 (India)
India, Bangalore
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
