딥엑스에서 고속 인터페이스 PHY IP 설계 및 통합을 담당할 엔지니어를 채용합니다. 고속 아날로그/혼성 신호 설계 또는 PHY RTL 설계 분야에서 5년 이상의 경력이 필수입니다. AI 반도체 SoC 개발 경험과 LPDDR, PCIe, MIPI 프로토콜에 대한 깊은 이해를 갖춘 분을 찾습니다. 세계적인 NPU 기술을 선도하는 환경에서 혁신을 함께할 인재를 기다립니다.
DEEPX is a forward-thinking Series D startup architecting the infrastructure for the Physical AI era.
By delivering the world’s most energy-efficient NPU technology, we are solving the critical power and heat challenges of Generative AI to bring super-intelligence to every device, everywhere.
Our global leadership is validated by our record-breaking recognition as a multi-year CES Innovation Award honoree (2024 & 2026) and being named the 2024 Frost & Sullivan Company of the Year in the NPU sector. With an enterprise value approaching 1 trillion KRW, DEEPX offers a unique pre-IPO
opportunity to join a market leader defining the new industry standard for the $70B AI semiconductor market.
We are currently scaling toward mass production of our flagship DX-M1 (Samsung 5nm) with over 50 global projects scheduled, while engineering next-generation 2nm solutions to support 100B parameter Large Language Models (LLM) at the edge. ☞ Link
★ If you want to be part of world-class innovation? Please talk with us.
★Explore our journey: The DEEPX White Paper ☞ Link
□ PHY IP Integration: Lead the design, implementation, and integration of high-speed interface PHY IPs (such as LPDDR4/5, PCIe Gen4/5, MIPI D-PHY/C-PHY, etc.) for AI semiconductor SoCs.
□ Signal & Power Integrity (SI/PI): Conduct signal integrity and power integrity simulations to ensure robust high-speed data transmission and reliable power delivery.
□ Post-Silicon Validation: Participate in silicon bring-up, debugging, and characterization of PHY IPs to ensure compliance with industry standards.
□ Vendor Collaboration: Coordinate with external IP vendors and foundries to optimize PHY performance and manage technical requirements.
□ Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Electronic Engineering, Computer Engineering, or a related technical field.
□ Minimum 5+ years of relevant experience in high-speed analog/mixed-signal design or PHY-related RTL design.
□ Deep understanding of high-speed serial/parallel interface protocols (DDR, PCIe, MIPI, USB, etc.).
Experience in RTL design (Verilog/SystemVerilog) and logic synthesis for PHY control logic.
□ Strong analytical skills to debug complex mixed-signal issues and optimize PHY performance at the SoC level.
□ Advanced Nodes: Hands-on experience with advanced process nodes (7nm, 5nm, or below) at major foundries (Samsung, TSMC).
□ Proven track record of successful tape-outs and silicon validation for high-speed PHY IPs.
□ Familiarity with automotive functional safety standards (ISO 26262) and AEC-Q100 requirements.
Scripting: Proficiency in scripting languages (Tcl, Python, or Perl) for design automation and data analysis.
□ Excellent communication skills and the ability to work effectively in a cross-functional environment (RTL, Physical Design, and Board Design teams).
□ Application Review - (Phone Interview) - Technical Interview - Organizational Culture Fit Interview - CEO Interview - Reference Check / Compensation Discussion
※ The recruitment process may vary depending on the position and application content.
※ Candidates with less than 3 years of experience are required to submit their academic transcripts.
□ Full-time (3-month probationary period with 100% compensation)
□ Monday to Friday, 9:00 AM – 6:00 PM (Lunch break: 12:00 PM – 1:00 PM)
□ If any false information is found in the application or onboarding documents, the job offer may be withdrawn even after confirmation.
□ A 3-month probationary period applies after joining, with no reduction in salary or benefits.
□ 모든 정규직 입사자에게 연봉 수준의 스톡옵션 부여
□ 최신 사양 장비 및 최고의 근무 환경 제공 (최신 노트북, 높낮이 조절식 스탠딩 데스크, 모니터암, 듀얼모니터 등 제공)
□ 점심식사 + 아침 & 저녁식사 지원
□ 스낵, 아이스크림, 음료 등 사내 카페 무제한 간식 제공
□ 사우나가 포함된 피트니스 비용 지원
□ 연 1회 종합건강검진 지원 (배우자 포함)
□ 생일, 결혼기념일, 크리스마스이브 축하금 지급 및 조기퇴근 제공
□ 설/추석 명절 상여금 지급
□ 축하와 위로를 위한 경조휴가 및 경조금 지원
