딥엑스에서 PCIe Controller 및 Link Layer 설계를 담당할 엔지니어를 채용합니다. NPU SoC 개발 경험과 PCIe Gen4/5 프로토콜에 대한 깊은 이해가 필수입니다. Verilog/SystemVerilog를 활용한 RTL 설계 역량을 갖춘 분을 찾습니다. 세계적인 AI 반도체 기술을 선도하는 환경에서 성장할 기회입니다.
DEEPX is a forward-thinking Series D startup architecting the infrastructure for the Physical AI era.
By delivering the world’s most energy-efficient NPU technology, we are solving the critical power and heat challenges of Generative AI to bring super-intelligence to every device, everywhere.
Our global leadership is validated by our record-breaking recognition as a multi-year CES Innovation Award honoree (2024 & 2026) and being named the 2024 Frost & Sullivan Company of the Year in the NPU sector. With an enterprise value approaching 1 trillion KRW, DEEPX offers a unique pre-IPO
opportunity to join a market leader defining the new industry standard for the $70B AI semiconductor market.
We are currently scaling toward mass production of our flagship DX-M1 (Samsung 5nm) with over 50 global projects scheduled, while engineering next-generation 2nm solutions to support 100B parameter Large Language Models (LLM) at the edge. ☞ Link
★ If you want to be part of world-class innovation? Please talk with us.
★Explore our journey: The DEEPX White Paper ☞ Link
□ Design and implementation of PCIe Controller and Link Layer logic for NPU SoCs
□ Integration and verification of PCIe IP in RTL design
□ Development of PCIe protocol logic including configuration, flow control, and error handling
□ Performance optimization and validation of PCIe interfaces
□ Collaboration with verification, firmware, and system teams for end-to-end PCIe functionality
□ Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or related field
□ Strong understanding of PCIe protocol (Gen4/Gen5) and related standards
□ Proficiency in RTL design using Verilog/SystemVerilog
□ Experience in synthesis, timing analysis, and FPGA prototyping
□ Ability to analyze and debug hardware interface issues
□ Experience in high-speed interface design (e.g., PCIe, DDR, CXL, Ethernet)
□ Familiarity with verification methodologies such as UVM
□ Experience with simulation tools (VCS, ModelSim, etc.) and EDA environments
□ Knowledge of SoC architecture and hardware/software co-design
□ Strong problem-solving skills and ability to work in a fast-paced startup environment
□ Application Review - (Phone Interview) - Technical Interview - Organizational Culture Fit Interview - CEO Interview - Reference Check / Compensation Discussion
※ The recruitment process may vary depending on the position and application content.
※ Candidates with less than 3 years of experience are required to submit their academic transcripts.
□ Full-time (3-month probationary period with 100% compensation)
□ Monday to Friday, 9:00 AM – 6:00 PM (Lunch break: 12:00 PM – 1:00 PM)
□ If any false information is found in the application or onboarding documents, the job offer may be withdrawn even after confirmation.
□ A 3-month probationary period applies after joining, with no reduction in salary or benefits.
□ 모든 정규직 입사자에게 연봉 수준의 스톡옵션 부여
□ 최신 사양 장비 및 최고의 근무 환경 제공 (최신 노트북, 높낮이 조절식 스탠딩 데스크, 모니터암, 듀얼모니터 등 제공)
□ 점심식사 + 아침 & 저녁식사 지원
□ 스낵, 아이스크림, 음료 등 사내 카페 무제한 간식 제공
□ 사우나가 포함된 피트니스 비용 지원
□ 연 1회 종합건강검진 지원 (배우자 포함)
□ 생일, 결혼기념일, 크리스마스이브 축하금 지급 및 조기퇴근 제공
□ 설/추석 명절 상여금 지급
□ 축하와 위로를 위한 경조휴가 및 경조금 지원
