딥엑스에서 고속 인터페이스 SI/PI 엔지니어를 채용합니다. NPU 및 고성능 AI 반도체의 전력 무결성(PDN)과 신호 무결성(SI) 분석을 담당하며, 5년 이상의 SI/PI 실무 경험과 Ansys, Cadence Sigrity 등 시뮬레이션 툴 활용 능력이 필수입니다. 세계 최고 수준의 NPU 기술을 함께 만들어갈 전문가를 찾습니다.
DEEPX is a forward-thinking Series D startup architecting the infrastructure for the Physical AI era.
By delivering the world’s most energy-efficient NPU technology, we are solving the critical power and heat challenges of Generative AI to bring super-intelligence to every device, everywhere.
Our global leadership is validated by our record-breaking recognition as a multi-year CES Innovation Award honoree (2024 & 2026) and being named the 2024 Frost & Sullivan Company of the Year in the NPU sector. With an enterprise value approaching 1 trillion KRW, DEEPX offers a unique pre-IPO
opportunity to join a market leader defining the new industry standard for the $70B AI semiconductor market.
We are currently scaling toward mass production of our flagship DX-M1 (Samsung 5nm) with over 50 global projects scheduled, while engineering next-generation 2nm solutions to support 100B parameter Large Language Models (LLM) at the edge. ☞ Link
★ If you want to be part of world-class innovation? Please talk with us.
★Explore our journey: The DEEPX White Paper ☞ Link
As an SI/PI Engineer at DeepX, you will be responsible for ensuring the electrical integrity of our cutting-edge AI chip environments. You will focus on the analysis and optimization of high-speed interfaces and robust Power Delivery Networks (PDN) across the entire hardware ecosystem—from Silicon and Package to the System Board. Your critical mission will be ensuring our NPU solutions maintain peak performance, signal fidelity, and rock-solid power stability under extreme computational loads and sudden switching events.
□ PDN & Power Integrity Analysis: Perform comprehensive PDN analysis including DC/AC frequency-domain analysis (Target Impedance profiling) and time-domain transient simulations to guarantee stable power delivery from the VRM to the die.
□ NPU Transient Power Management: Analyze and mitigate inrush current and severe $di/dt$ noise caused by the simultaneous switching of massive digital blocks (e.g., MAC arrays) in NPU architectures. Establish and optimize on-die, package, and board-level decoupling capacitor (Decap) strategies to prevent Dynamic Voltage Drop (DVD) and Ground Bounce.
□ SI Modeling & Simulation: Perform comprehensive Signal Integrity (SI) simulations for high-speed interfaces (LPDDR4/5, PCIe Gen4/5, MIPI, etc.), ensuring optimal eye diagrams and jitter margins.
□ System-Level Co-Simulation: Conduct Chip-Package-Board (CPB) co-simulations using CPM (Chip Power Model) or equivalent methodologies to evaluate and mitigate cross-talk, EMI/EMC issues, thermal-electrical coupling, and IR drop.
□ Design Optimization: Establish design guides for PCB/Package stack-ups, high-speed routing, and optimal Decap placement (using optimization tools) to meet strict noise and jitter budgets.
□ Validation & Correlation: Collaborate with the hardware team to perform lab measurements (using Oscilloscopes, VNA, TDR, and active probes) and correlate physical data with simulation results.
□ Bachelor’s degree in Electrical Engineering, Electronic Engineering, or a related technical field.
□ 5+ years of hands-on experience in SI/PI analysis for high-speed digital and high-power IC designs.
□ In-depth knowledge of transmission line theory, S-parameters, PDN concepts, and power supply noise (SSN, DVD).
□ Proficiency in industry-standard simulation tools including Ansys (SIwave, HFSS, RedHawk for CPM integration), Cadence Sigrity (PowerSI, PowerDC, OptimizePI), or Keysight (ADS, PIPro). Experience with SPICE-level transient simulations is highly preferred.
□ Ability to use high-frequency measurement equipment to validate signal quality and power stability (e.g., measuring PDN impedance and transient droop).
□ Master’s or Ph.D. with a focus on Electromagnetics, Power Electronics, or High-Speed Circuit Design.
□ NPU/GPU Power Design: Direct experience resolving extreme transient power challenges in highly parallel computing architectures like NPUs, GPUs, or high-end SoCs.
□ Specific Protocol Expertise: Experience with LPDDR5x or PCIe Gen5/6 interface design and verification.
□ Packaging Knowledge: Understanding of advanced packaging technologies (Flip-chip, 2.5D/3D IC, SiP) and their impact on signal and power integrity.
□ Scripting Skills: Proficiency in Python or MATLAB for automation of simulation workflows and data post-processing.
□ Communication: Strong problem-solving skills and the ability to communicate technical concepts clearly across multi-functional teams (SoC Design, Package, and System).
□ Application Review - (Phone Interview) - Technical Interview - Organizational Culture Fit Interview - CEO Interview - Reference Check / Compensation Discussion
※ The recruitment process may vary depending on the position and application content.
※ Candidates with less than 3 years of experience are required to submit their academic transcripts.
□ Full-time (3-month probationary period with 100% compensation)
□ Monday to Friday, 9:00 AM – 6:00 PM (Lunch break: 12:00 PM – 1:00 PM)
□ If any false information is found in the application or onboarding documents, the job offer may be withdrawn even after confirmation.
□ A 3-month probationary period applies after joining, with no reduction in salary or benefits.
□ 모든 정규직 입사자에게 연봉 수준의 스톡옵션 부여
□ 최신 사양 장비 및 최고의 근무 환경 제공 (최신 노트북, 높낮이 조절식 스탠딩 데스크, 모니터암, 듀얼모니터 등 제공)
□ 점심식사 + 아침 & 저녁식사 지원
□ 스낵, 아이스크림, 음료 등 사내 카페 무제한 간식 제공
□ 사우나가 포함된 피트니스 비용 지원
□ 연 1회 종합건강검진 지원 (배우자 포함)
□ 생일, 결혼기념일, 크리스마스이브 축하금 지급 및 조기퇴근 제공
□ 설/추석 명절 상여금 지급
□ 축하와 위로를 위한 경조휴가 및 경조금 지원
