GPU Validation Engineer

Job Details:

Job Description:

Are you passionate about working with a team that integrates and brings up innovative graphics technologies and tests its limits? You will be working with highly motivated Graphics engineers who collaborates with diverse talents to achieve best in class gaming experience through integrated solutions and increase productivity card for AI, HPA, and cloud gaming. Our Graphics Engineering Organization has opportunities for you. As part of Pre-Silicon Validation team, you get to work on the newest technologies and features associated with Intel graphics. As a GPU Pre-Silicon Validation Engineer, you will Define, develop, and perform functional validation for GPUs, focusing on validation of interaction of GPUs, media, display and system level features. Apply various hardware and software level tools and techniques to ensure validation coverage to meet performance, power, and area goals. Review proposed design changes to assess impact on validation plans, tasks, and timelines. Develop GPU validation methodologies, execute validation plans, and collaborate with other engineers for design optimization, troubleshooting, and failure analysis. Perform pre-silicon debug to identify root causes and resolve all functional and triage failures for GPU issues. Test interactions between various GPU features using validation infrastructure. Influence pre-silicon validation infrastructure (behavioral checkers, trackers, waveform captures) and test environment used in validation testing. Publish GPU validation reports summarizing all validation activities performed, review results, and communicate to relevant teams. Work with architecture, design, verification, platform teams to maintain and improve debug, validation test strategy, methodologies, and processes for graphics interfaces and to meet desired product specifications.

Behavioral skills we are looking for:

• Ability to work collaboratively with cross-functional teams.
• Effective communication and reporting skills.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Bachelor's degree in computer science, electrical engineering, computer engineering or related STEM degree and 6+ years of industry experience OR
• Master's degree in computer science, electrical engineering, computer engineering or related STEM degree and 4+ years of industry experience.

The years of experience listed above must include:

• Computer Architecture Knowledge and GPU Microarchitecture Fundamentals
• Knowledge of GPU functional testing.
• Experience in 1 or more of the following areas:
• Experience with pre-silicon Validation techniques, tools and debug.
• IP Test Writing and Test Plans.
• Software programming in C/C++ and/or scripting (such as PythonSV).
• Validation Protocols and Strategy Development

Preferred Qualifications:

• Familiarity with PCIe standards and compliance requirements.
• Deep understanding of HW/FW flows.
• Strong troubleshooting and analytical skills.
• Experience and hands on skills with LTB, ITP, Logic Analyzers, Oscilloscopes, Scan dumps, and in-circuit Emulators

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, California, Folsom

Additional Locations:

US, California, Santa Clara

Business group:

At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.