인텔에서 차세대 SoC/CPU 설계 및 검증을 담당할 인턴을 모집합니다. EECS 관련 학사 과정 중인 학생을 대상으로 하며, VLSI 설계 및 시스템 베릴로그(System Verilog) 지식을 보유한 분을 우대합니다. 하이브리드 근무 환경에서 실무 역량을 쌓을 수 있는 기회입니다.
In this position, you will be involving in the training, design and development of next generation SOC/CPU for wide range of Intel products and Internet of Things. Your responsibilities will include one or some of the following but not limited to:
Assist design unit owner in Register Transfer Level RTL model functional validation. Use CAD tool extensively to simulate logic behavior and circuit performance and direction of physical design for next generation, deep sub-micron embedded circuit solutions. Verify the circuit behavior against the original simulation model and first silicon.
Define VLSI Structural Design methodology and developing design flows. Implement structural physical designs, such as synthesis, floor planning, power-grid and clock tree designs, timing budgeting and closure, place and route, RC-extraction and integration. Verify structural physical designs, such as functional equivalency, timing/performance, noise, layout design rules, reliability and power.
Responsible for Integration of Third party IPs -- Synthesis, functional and/or timing convergence, and pre and post-si debug of IPs developed by various external vendors as well as within the company. Handling of signals crossing power planes and clock domains, industry standard protocols including hardware and software details dealing with Memory LPDDR, storage eMMC, SATA, UFS, peripherals PCIe, USB, and MIPI interfaces in SOC devices. System integration dealing with Si/ Platform/ FW/ MW/ drivers/ OS/ Apps on Android and Windows-based tablets and phones.
Responsible to validate and integrate third party IPs ensuring they meet product specification and functionality before they are productized into physical chip. Required to work very closely with design teams and architects to implement the low-level RTL design to ensure overall good functionality of the chip. Develop specific test environment/platform, validation methodology and test plan to validate SOC design by identifying and exercising boundary conditions and special cases in an effort to break the chip to find that last elusive bug.
Oversees definition, design, verification, and documentation for SoC System on a Chip development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and sub-systems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.
You must possess the below minimum qualifications to be initially considered for this position:
Students pursuing a Bachelor degree in EECS or related major with good CGPA
Good communication skills and proficient in English
Knowledge on Unix, VLSI Design, SOC/PC Architecture, System Verilog is major plus
Student / Intern
Shift 1 (Malaysia)
Malaysia, Penang
Malaysia, Kulim
Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
N/A
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
