인텔의 P-Core 설계 팀에서 차세대 CPU 개발을 이끌 회로 설계 리드를 모집합니다. 메모리 설계(SRAM/RF/ROM) 및 정적 타이밍 분석에 대한 깊은 전문성이 필수입니다. 8년 이상의 관련 경력이 요구되며, 고속·저전력 디지털 설계 방법론을 주도하게 됩니다. 하이브리드 근무가 가능하며 최신 공정 기술을 다루는 핵심적인 역할을 수행합니다.
You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for leading the design analysis and methodologies of the different types of memory blocks and data path subsystems. Your responsibilities will include but not limited to: 1. Responsible for methodology enablement for memory blocks to meet over 5GHz Freq and low-power digital designs with optimal area. 2. In depth understanding of different memory design concepts ((SRAM/RF/ROM). 3. Expertise in Static timing analysis concepts. 4. Close work with Layout and Floor planning teams. 5. Back-end design implementation of new features. 6. Expertise in Memory post silicon analysis. 7. Good understanding of statistical variation.
You must possess a Masters Degree in Electrical or Computer Engineering with atleast 8 or more years of experience in related field or a Bachelors Degree with atleast 10 years of experience. Technical Expertise in synthesis, P and R tools preferred. Preferred Qualifications: 1. Digital Design Experience, with High Speed, Low Power. 2. Familiarity with Verilog. 3. Tcl, Perl, Python scripting. 4. Good understanding of spice simulations and analysis 5. Strong verbal and written communication skills.
Experienced Hire
Shift 1 (India)
India, Bangalore
Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
N/A
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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