인텔에서 아날로그 및 혼합 신호 회로 설계를 담당할 엔지니어를 채용합니다. 고급 CMOS 공정 기반의 전력 공급 기술 개발이 핵심이며, Cadence 설계 툴 활용 능력과 관련 분야 실무 경력이 필수입니다. 혁신적인 전력 관리 시스템을 설계하며 글로벌 기술 리더십을 경험할 수 있는 기회입니다.
The Role and Impact Are you passionate about driving innovation in analog and mixed-signal circuit design? Join our team to develop groundbreaking power delivery technologies that transform how people interact with technology. As an Analog Circuit Design Engineer, you will be at the forefront of designing and optimizing analog circuits in advanced process nodes. Your contributions will directly influence Intel's mission to deliver high-performance, energy-efficient products that enrich the lives of people worldwide. Key Responsibilities - Design and develop complex analog and mixed-signal circuits for advanced CMOS technologies, focusing on power delivery and mixed-signal IPs. - Perform circuit design, simulation, and optimization to meet power, performance, area, timing, and yield goals. - Execute analog block floor-planning and extract chip parameters to ensure robust and efficient designs. - Develop and implement test plans to verify circuit designs against microarchitecture specifications. - Conduct post-layout simulations with extracted parasitics and fine-tune designs to meet required specifications. - Collaborate cross-functionally with architecture, layout, and validation teams to optimize circuit functionality and resolve design challenges. - Evaluate experimental test data and iterate designs to improve performance, reduce leakage, and enhance robustness.
Minimum Qualifications - Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with 3+ years of relevant experience, or a Master's degree with 2+ years of experience, or a PhD with no prior experience. - Proficiency in analog or mixed-signal circuit design, including amplifiers, LDOs, PLLs, ADCs, and similar components. - Practical knowledge of analog layout techniques, including floor-planning, matching, shielding, and parasitic optimization. - Experience with industry-standard CAD tools such as Cadence Spectre/AMS Designer/Virtuoso and StarRC for schematic design and simulation. Preferred Qualifications - Expertise in power delivery and power management systems. - Hands-on experience transitioning analog and mixed-signal circuits from design to layout to silicon prototyping. - Familiarity with tools and methodologies for analog validation and debugging. Come be a part of a team where your expertise will contribute to cutting-edge innovations that shape the future of technology. Apply today to make your mark on Intel's legacy of excellence in analog circuit design.
Experienced Hire
Shift 1 (United States of America)
US, California, Santa Clara
US, Massachusetts, Beaver Brook, US, Oregon, Hillsboro, US, Texas, Austin
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-200,340.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
