システムモデリングエンジニア
ソフトウェアエンジニア正社員シニア · 4年以上ベンガルール出社
224Gbps SerDes PHYのシステムアーキテクチャおよび行動モデリングを主導し、性能分析と最適化を担当します。学士12年以上、修士8年以上、または博士4年以上の関連経験が必須です。アナログ回路設計および高速設計技術に関する専門知識が求められます。勤務形態はオンサイトです。
224Gbps SerDes PHYのシステムアーキテクチャおよび行動モデリングを主導し、性能分析と最適化を担当します。学士12年以上、修士8年以上、または博士4年以上の関連経験が必須です。アナログ回路設計および高速設計技術に関する専門知識が求められます。勤務形態はオンサイトです。
The Role and Impact: As an Analog and Mixed Signal IP Architect, you will play a pivotal role in shaping the future of Intel's cutting-edge technologies. You will be responsible for driving innovative architectures and algorithms that define the next generation of System-on-Chip (SoC) independent analog and mixed signal IPs. We are seeking an experienced SerDes PHY System Modeling Engineer to lead and support the architecture, modeling, and performance analysis of 224Gbps SerDes IP. This role focuses on endtoend PHY system modeling, including electrical channel, transmitter (TX), receiver (RX), equalization strategies, clocking, and jitter/noise analysis, enabling robust silicon implementation for nextgeneration ASICs and SoCs. Key Responsibilities: System Architecture and Modeling: Develop endtoend behavioral models for 224Gbps SerDes PHYs across TX, channel, and RX. Build statistical and timedomain system models to evaluate BER, eye margins, and link robustness Define PHY performance budgets (jitter, noise, ISI, crosstalk, insertion loss) Model and optimize PAM4 signaling at very high data rates Channel and Equalization Analysis: Model electrical channels including packages, PCBs, connectors, and crosstalk. Develop and tune TX FIR, RX CTLE, DFE, and adaptive equalization algorithms Perform Swept channel analysis to ensure compliance across worstcase conditions Support cooptimization of channel, package, and PHY architecture Clocking, Jitter and Noise Analysis: Model PLL/DLL behavior, phase noise, and jitter transfer functions Perform jitter decomposition (RJ, DJ, PJ, SJ) and bathtub curve analysis Analyze CDR performance, loop dynamics, and tolerance to jitter/noise sources Compliance and Standards Support: Support modeling and interpretation of industry standards (IEEE, OIF, etc.), including 224Grelated efforts Define channel and compliance test methodologies Align system models with compliance test specifications and silicon validation strategies Work closely with circuit designers, DSP/algorithm teams, package/PCB engineers, and validation teams Translate systemlevel requirements into blocklevel and circuitlevel specs Support silicon bringup and debug through correlation of lab data with system models
Minimum Qualifications:
Preferred Qualifications:
Take the next step in your career by applying today. Join us in shaping the future of analog and mixed signal IP and making a lasting impact on the semiconductor industry.
Experienced Hire
Shift 1 (India)
India, Bangalore
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
N/A
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.