IntelではSoC Design Engineering Managerを募集しています。Physical Designにおける18年以上の経験、大規模チームの管理実績、および複数のSoC tapeoutを成功させた経験が必須です。RTL-to-GDSワークフローに関する深い知識と優れたリーダーシップを持つ方を求めています。
Intel Central Engineering Group is seeking SoC Design Engineering Manager to join our dynamic team and contribute to the development of cutting-edge custom IP and SoC designs for Intel products and Intel Custom ASIC Customers. In this role, you will play a pivotal part in translating RTL to GDS, enabling manufacturing-ready design databases that drive innovation in products. Leads and manages silicon design teams that span across more than one area of functional development including logic design, verification, circuit design, and/or physical design for an IP, subsystem, SoC, and/or discrete chip. Manages the engineering team resources, their functions, activities, responsibilities, and driving continuous improvement and silicon quality standards. Conducts design reviews to ensure key factors such as power, performance, area, and cost are meeting requirements. Works to continuously to improve silicon development processes and architecture definition across areas of silicon design. Oversees and reviews design verification test results, data analysis, issue tracking, root cause analysis, and drives corrective actions implementation for silicon design. Works closely across IP and SoC development teams to design complex projects, ensure quality, drive performance, and design implementation. Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results. Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment.
Minimum Qualifications: - Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field with 18+ Years of experience in Physical Design execution. - Excellent track record in managing large physical design teams and delivering to multiple SoC tapeout on advanced technology nodes. - Deep knowledge in RTL-to-GDS workflows, including synthesis, place and route, and static timing analysis. - Track record of building large SOC design teams and demonstrating engineering excellence in physical design execution. - Demonstrated ability to collaborate across cross functional spanning across geos to achieve the tapeout goals. - Strong critical thinking and problem-solving skills to manage complex design challenges. - Excellent communication and organizational abilities to coordinate across disciplines. - A passion for innovation and continuous improvement in design execution and KPIs.
Experienced Hire
Shift 1 (India)
India, Bangalore
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
