シニアVLSI設計エンジニア
ハードウェアエンジニア正社員シニア · 5年以上イスラエル, Haifaハイブリッド
半導体プロセス技術と設計手法を改善し、PPAを最適化する業務を担当します。電気工学またはコンピュータ工学の学士号以上が必須であり、VLSI物理設計における5年以上の実務経験が求められます。PythonおよびTCLを用いたスクリプト作成能力が必要です。技術チームのメンタリングも行い、ハイブリッド勤務形態で業務を行います。
半導体プロセス技術と設計手法を改善し、PPAを最適化する業務を担当します。電気工学またはコンピュータ工学の学士号以上が必須であり、VLSI物理設計における5年以上の実務経験が求められます。PythonおよびTCLを用いたスクリプト作成能力が必要です。技術チームのメンタリングも行い、ハイブリッド勤務形態で業務を行います。
Our team is dedicated to optimizing Intel's process technology to meet evolving Intel designs needs. We drive continuous improvements in silicon designs and methodologies, working at the intersection of process development and design implementation. By partnering closely with Core and SoC design teams, we capture and optimize process requirements to enable competitive, high-performance products.
As a Senior VLSI Process Design Engineer, you will play a key role in achieving best-in-class power, performance, and area (PPA) for Intel IPs. You will conduct experiments to identify challenges and optimization opportunities in Intel's process technology, evaluate device, cells and blocks, and translate findings into actionable recommendations that influence strategic decision-making and product direction.
Conduct experiments to identify potential challenges and optimization opportunities in Intel's process technology.
Drive continuous improvements to enhance Intel's designs and methodologies across advanced technology nodes.
Define methodologies and build tools to optimize PPA of Intel IPs.
Analyze PPA results, derive insights, and communicate findings and recommendations to stakeholders, contributing to strategic decision-making and project direction.
Collaborate with Core and SoC design teams to capture and optimize process requirements that enable competitive designs and products.
Mentor and guide technical teams, foster growth and best practices.
BSc or MSc in Electrical Engineering or Computer Engineering.
5+ years of hands-on experience in VLSI physical design, with a proven track record of successful projects on advanced technology nodes.
Basic scripting languages knowledge such as Python and TCL.
Good familiarity with physical design implementation flows and techniques, including floorplanning, placement, routing, and timing closure.
Knowledge at the cell and transistor level.
Deep understanding of the various factors impacting PPA trade-offs.
Experience mentoring technical teams.
Experienced Hire
Shift 1 (Israel)
Israel, Haifa
Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
N/A
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.