Job Details:

Job Description:

The Role and Impact

As a Physical Design Engineer, you will play a pivotal role in the implementation of custom IP and SoC designs, ensuring they are optimized for manufacturing and performance.
Your day-to-day responsibilities will involve executing the physical design flow from RTL to GDS, including synthesis, place and route, timing analysis, and verification.
By bringing your expertise to this critical part of chip design, you'll contribute to delivering high-performance, reliable, and innovative products that drive Intel's technological advancements.

Business group

You will be joining Intel's cutting-edge design engineering team, which focuses on creating world-class solutions for silicon design and manufacturing. The group collaborates across domains to develop advanced methodologies that support Intel's mission to produce high-performing, energy-efficient, and scalable products. With a culture rooted in innovation and teamwork, the group plays a key role in shaping Intel's leadership in semiconductor technology.

Key Responsibilities

Conduct end-to-end physical design implementation of custom IP and SoC designs from RTL to GDS.
Execute synthesis, floor planning, place and route, and clock tree synthesis to meet design specifications.
Perform static timing analysis, noise glitch/signal integrity analysis, and power distribution optimization.
Analyze verification results, including equivalence checks, power integrity, reliability checks, and timing closure, and make recommendations for resolving violations.
Collaborate with cross-functional teams to optimize design parameters such as power, area, and frequency.
Contribute to the development and enhancement of physical design methodologies, flows, and automation for improved efficiency and scalability.

Qualifications:

Minimum Qualifications

Bachelor's degree in a specialized field such as Electrical Engineering, Computer Engineering, or similar with 8+ years of hands-on experience in physical design OR Master's degree with 6+ years of experience OR PhD with 4+ years of experience.
Proficiency in key physical design tools and flows, including synthesis, FC / Innovus place and route, static timing analysis, and verification methodologies.
Expertise in design optimization techniques, power planning, clock tree synthesis, and low-power design methodologies.
Demonstrated ability to handle EDA tools with the latest AI/ML capabilities for design automation.
Strong scripting skills for flow automation and process efficiency (e.g., Python, Perl, TCL).

Preferred Qualifications

Experience in DFT physical design implementation and formal verification flows.
Knowledge of advanced floor planning techniques and macro placement.
Strong problem-solving ability and collaborative mindset.
Commitment to driving innovation in design methodologies and process improvement.
Exposure or Usage of Agentic AI & ML tools

Your expertise and skills are essential to Intel's success in delivering groundbreaking technology. We invite you to be part of a team that thrives on innovation, collaboration, and making a meaningful impact in the semiconductor industry.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

シニア・フィジカル・デザイン・エンジニア

Job Details:

Job Description:

The Role and Impact

Business group

Key Responsibilities

Qualifications:

Minimum Qualifications

Preferred Qualifications

Job Type:

Shift:

Primary Location:

Additional Locations:

Posting Statement:

Position of Trust

Work Model for this Role

Job Details:

Job Description:

The Role and Impact

Business group

Key Responsibilities

Qualifications:

Minimum Qualifications

Preferred Qualifications

Job Type:

Shift:

Primary Location:

Additional Locations:

Posting Statement:

Position of Trust

Work Model for this Role