IntelはSenior Design Verification Engineerを募集しています。SystemVerilogおよびUVM手法に精通し、5年以上の経験を持つ専門家を求めています。主な業務は、IPブロック検証の計画、インターコネクトプロトコルの検証、およびデバッグです。RAS機能の検証経験が必須であり、ジュニアエンジニアのメンタリングも担当します。勤務地はインドのバンガロールで、オンサイト勤務が必須です。
The Role and Impact: Intel is seeking a Design Verification Engineer for the Silicon Chassis team. In this role, you will independently own verification of interconnect and chassis IP blocks from planning through coverage closure, operating with minimal guidance. You will build and drive robust verification plans, develop scalable reusable environments, and take direct accountability for quality and schedule on your assigned blocks. You will work closely with architecture, design, and software teams and are expected to contribute across traditional discipline boundaries. This role requires strong DV depth, solid protocol knowledge, hands-on coding strength, and growing ability to mentor junior engineers. AI-assisted workflows are part of everyday development here. Consistent execution against schedule and quality goals is expected. Key Responsibilities: - Own verification planning and execution for assigned IP blocks and features at IP and subsystem level; drive test plans through coverage closure with direct accountability for quality. - Build scalable verification environments with reusable testbenches, checkers, constrained-random tests, and debug infrastructure; take ownership of the verification collateral you deliver. - Collaborate closely with architecture, design, and software teams on spec reviews, feature clarification, bug triage, and closure; contribute outside strict DV boundaries when needed to unblock progress, - Analyze simulation failures, root-cause issues quickly, and drive fixes to closure with clear technical communication, own debug for your blocks end-to-end. - Drive functional coverage planning and coverage closure for assigned blocks; contribute to quality signoff with increasing independence. - Continuously improve verification automation, regression quality, and development efficiency. - Begin mentoring junior engineers on verification practices, debugging techniques, and code quality.
Minimum Qualifications: - BS/MS in Electrical Engineering, Computer Science, or related field, with 5+ years of relevant experience in design verification; solid background in IP-level DV with meaningful exposure to subsystem-level verification. - Strong proficiency in SystemVerilog and UVM methodology. - Hands-on experience verifying RAS features - error injection, fault propagation, error logging, recovery sequences. - Strong and growing expertise in interconnects and bus protocols such as AMBA AXI/ACE/CHI, PCIe, CXL, or UCIe; working understanding of cache coherency and memory consistency models. - Solid understanding of SVA (SystemVerilog Assertions) for protocol compliance checking. - Experience building coverage models and driving test plans to closure. - Strong debugging skills - ability to trace transactions across multiple protocol domains. Preferred Qualifications: - Experience with telemetry/performance counter verification or debug/trace infrastructure verification. - Experience with AI-assisted verification workflows (LLM-generated RTL/TB code review). - Prior work on Intel fabric or SoC interconnect IPs is a strong plus. At Intel, we are committed to fostering an inclusive workplace where innovation and diverse perspectives thrive. Join us to make a profound impact on the technology that shapes our world.
Experienced Hire
Shift 1 (India)
India, Bangalore
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
N/A
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
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