Job Details:

Job Description:

Our Team

Join us to help build the next generation of AI hardware solutions. You will be part of a highly skilled, agile team developing cutting-edge hardware for the AI domain, where we push the boundaries of what silicon can do for emerging AI workloads. With a startup-like culture, we move quickly and give engineers the opportunity to drive significant technical and business impact.

Our team is responsible for taking silicon products through the full product lifecycle, from concept and design through qualification and into high-volume manufacturing. Our scope covers silicon test (ATE), system-level test (SLT), and production operations and supply chain, working closely with Design, DFT, Validation, and Product Engineering teams, as well as external partners including foundries, OSATs, and test hardware vendors.

We are building this team from scratch within Intel. These first roles are the foundation we plan to grow from, so you'll help shape how the team tests, scales, and operates. You'll have a high degree of independence to define your area, backed by the resources and stability of a large company.

Key Responsibilities

Define the ATE test strategy and drive HW and DFT requirements to support it.
Lead implementation of complete ATE test solutions.
Define the test plan and align with DFT on content, coverage, and deliverables.
Partner with Test Application Engineering on tester configuration, test program content, and test flow development.
Own test program execution including release schedules, procedures, content definitions, and delivery for qualification and production.
Define, procure, and bring up ATE hardware including load boards and probe cards.
Optimize ATE test solutions for high-volume manufacturing and deployment to OSATs.
Drive yield improvement, test cost optimization, and manufacturing readiness.

Qualifications:

Minimum Qualifications

Bachelor's degree in a scientific field such as Electrical Engineering, Computer Engineering, Physics, Mathematics, Computer Science, or a related discipline.
Minimum 8 years of experience in ATE test development, silicon test, product engineering, or related semiconductor test environments.
Strong familiarity with the ASIC ATE environment, ideally Teradyne or Advantest testers, HVM handlers, and test hardware (load boards and probe cards).
Hands-on ATE content development and a solid understanding of DFT-driven and functional test concepts, including ATPG/Scan, MBIST, and high-speed I/O testing such as PCIe, SerDes, and DDR.
Good understanding of OSAT production environments, including handlers, testers, test hardware, and manufacturing capacity considerations.
Broad silicon knowledge spanning electrical, mechanical, logical, and physical domains.
Experience with test program environments such as IG-XL and/or SmarTest.
Experience with scripting languages such as Python and/or Perl.
Experience using data and yield analysis tools such as JMP, Spotfire, or similar.
Strong leadership skills with the ability to align cross-functional stakeholders and manage vendor and OSAT relationships.

Preferred Qualifications

Experience as a Tech Lead, Test Lead, ATE Lead, or similar technical leadership role.
Practical implementation experience in AI-assisted design or engineering environments.
Experience bringing new silicon products from first silicon through high-volume manufacturing.

Job Type:

Experienced Hire

Shift:

Shift 1 (Israel)

Primary Location:

Israel, Haifa

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

シニアATEテストエンジニア

Job Details:

Job Description:

Our Team

Key Responsibilities

Qualifications:

Minimum Qualifications

Preferred Qualifications

Job Type:

Shift:

Primary Location:

Additional Locations:

Posting Statement:

Position of Trust

Work Model for this Role

Job Details:

Job Description:

Our Team

Key Responsibilities

Qualifications:

Minimum Qualifications

Preferred Qualifications

Job Type:

Shift:

Primary Location:

Additional Locations:

Posting Statement:

Position of Trust

Work Model for this Role