Intelではプリンシパル SerDes アーキテクトを募集しています。高速IO PHYアーキテクチャの定義とアナログ回路設計を主導し、アナログ回路設計分野で10年以上の経験が必須です。TX/RXブロックおよび低消費電力設計に関する深い専門知識が求められます。技術的リーダーシップを発揮し、次世代の設計を牽引する人材を求めています。ハイブリッド勤務が可能で、業界最高水準の報酬を提供します。
The Role and Impact
As a Principal Engineer in Analog Circuit Design, you will be at the forefront of innovation, driving technical excellence and advancing Intel's leadership in analog and mixed-signal IPs. This role is pivotal in defining and delivering cutting-edge designs in advanced process nodes, ensuring optimal performance, power efficiency, and robustness. As a recognized domain expert, you will influence technical direction across Intel and the broader industry while mentoring other technical leaders and fostering a community of innovation.
Key Responsibilities
Lead architecture definition and development of next-generation high-speed IO PHYs with industry-leading PPA metrics
Design, develop, and optimize analog circuits, including TX/RX blocks, in advanced process nodes for analog and mixed-signal IPs.
Create floorplans, extract chip parameters, and simulate analog behavior models to meet performance, power, and area goals.
Develop comprehensive test plans, verify designs against microarchitecture specifications, and evaluate test results to ensure optimal functionality.
Optimize circuit performance, power, area, and yield, identifying and resolving design challenges.
Collaborate with architecture and layout teams to design robust circuits with best-in-class electrical capabilities.
Provide technical leadership across Intel and the industry by developing technical strategies and aligning them with organizational goals.
Act as a mentor and role model for other technical leaders, fostering growth, providing guidance, and cultivating a community of technical excellence.
Serve as a change agent by driving innovation, relentless execution, and delivering leadership solutions to market.
Minimum Qualifications
Preferred Qualifications
Proven track record of technical leadership in analog circuit design, influencing direction across organizations or the industry.
Familiarity with SerDes fundamentals
Familiarity with UCIe and PCIe specifications
Strong understanding of analog architecture, layout optimization, and best practices in analog circuit robustness and electrical capabilities.
Excellent strategic thinking and problem-solving skills, with the ability to align technical vision with organizational goals.
Experience mentoring and developing technical talent, fostering collaboration, and driving innovation across teams.
Join Intel and be part of a team that is shaping the future of technology. If you are ready to lead, innovate, and make a difference, we encourage you to apply today.
Experienced Hire
Shift 1 (United States of America)
US, California, Santa Clara
US, Arizona, Phoenix, US, California, Folsom, US, Oregon, Hillsboro
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
