Intelは、RTL-to-GDSIIフローを支援する物理設計インターンを募集しています。学生を対象とし、半導体物理学およびVLSI設計の基礎知識が必須です。主な業務は、フロアプランニング、配置、配線、および物理検証です。PythonやTclによるスクリプト作成能力が求められ、週4日のオンサイト勤務が必須となります。
A Physical Design Intern assists in the semiconductor RTL-to-GDSII flow, learning to transform circuit designs into physical layouts for chip manufacturing. Interns work with senior engineers on floorplanning, placement, routing, and physical verification (DRC/LVS), using industry-standard EDA tools in UNIX/Linux environments.
• Layout & Implementation: Assist in floorplanning, block-level placement, and routing to meet aggressive power, performance, and area (PPA) goals.
• Physical Verification: Run Design Rule Checks (DRC) and Layout Versus Schematic (LVS) verifications to ensure the design meets foundry manufacturing requirements.
• Timing & Power Analysis: Learn to analyze cross-talk, noise, IR drop, and assist in sub-system level static timing analysis (STA).
• Scripting: Write and debug scripts (Python, Tcl, Perl) to automate data analysis and streamline the design flow.
Third-year or Final-year student currently pursuing a Bachelor's degree in Electrical Engineering, Computer Engineering, or VLSI Systems or a closely related field (Physics, Maths).
Be able to work onsite for 4 days per week.
Be able to commit to at least a 6-month internship program.
Strong verbal and written communication skills in English.
Fundamental understanding of semiconductor device physics, analog circuit theory, or digital VLSI design concepts.
Familiarity with UNIX/LINUX operating systems and basic programming skills.
Exposure to industry EDA tools (Cadence Innovus/Virtuoso, Synopsys ICCII/Fusion, Calibre) is a strong plus.
Attractive internship allowance
Training programs, opportunities to be involved in multinational projects.
Exciting extracurricular and sports programs for employees
Well-invested facilities, putting safety first.
Shuttle bus system at many places in Ho Chi Minh City, Binh Duong, Dong Nai.
High-quality cafeteria, lunch allowance.
Safe, stable and dynamic working environment.
Student / Intern
Shift 1 (Vietnam)
Vietnam, Ho_Chi_Minh_City
Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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