Job Details:

Job Description:

Join Intel as a Physical Design Engineer and play a pivotal role in shaping the future of custom IP and SoC designs. In this position, you will be instrumental in transforming designs from RTL to GDS, creating manufacturing-ready databases that enable groundbreaking innovations. Your expertise in physical design and verification will directly impact our ability to deliver high-performance, energy-efficient, and scalable silicon solutions for a wide range of applications. By contributing to the optimization of power, frequency, and area, you will help ensure our technology remains at the forefront of the semiconductor industry.

Key Responsibilities :

Perform end-to-end physical design implementation of custom IP and SoC designs, from RTL to GDS.
Conduct floor planning, power and clock distribution, and clock tree synthesis to optimize design performance and efficiency.
Execute place and route tasks, ensuring accurate pin and macro placement and robust layout cleanup.
Drive static timing analysis, power noise analysis, and reliability verification to achieve timing closure and design integrity.
Lead design verification and signoff processes, including formal equivalence verification, layout verification, and electrical rule checking.
Utilize industry-standard EDA tools to conduct multi-power domain analysis, DFT implementation, and low-power design methodologies.
Analyze verification results, resolving violations, and providing recommendations for current and future product architectures.
Continuously improve physical design methodologies and flow automation to enhance productivity and quality.

Qualifications:

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
3+ years of experience with a Bachelor's degree, or 2+ years of experience with a Master's degree in the structural and physical design domain.
Proficiency with RTL to GDS flows and industry-standard EDA tools for physical design and verification.
Expertise in clock design, clock tree synthesis, timing closure, floor planning, and multi-power domain analysis.
Hands-on experience with scripting languages such as Perl, TCL, or Unix shell for design automation.
Strong knowledge of digital design principles, CMOS processes, and low-power design techniques.

Preferred Qualifications

A postgraduate degree in Electrical Engineering, Computer Engineering, or Computer Science.
Demonstrated experience with standard-cell-based VLSI design methodology and advanced EDA tools.
Proven ability to lead technical development within a physical design team and mentor junior engineers.
Strong analytical skills and a track record of resolving complex design challenges in ASIC/SoC convergence.
Effective communication and collaboration skills to work across multidisciplinary teams.

Step into a role where your technical expertise and innovative thinking will drive meaningful advancements in semiconductor technology. Apply today to join Intel's mission to shape the future of computing and empower a connected world.

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

物理設計エンジニア

Job Details:

Job Description:

Key Responsibilities :

Qualifications:

Preferred Qualifications

Job Type:

Shift:

Primary Location:

Additional Locations:

Business group:

Posting Statement:

Position of Trust

Work Model for this Role

Job Details:

Job Description:

Key Responsibilities :

Qualifications:

Preferred Qualifications

Job Type:

Shift:

Primary Location:

Additional Locations:

Business group:

Posting Statement:

Position of Trust

Work Model for this Role