ミックスドシグナル設計検証エンジニア
ハードウェアエンジニア正社員ミドル · 4〜10年ベンガルールハイブリッド
ミックスドシグナルIP設計の機能検証を担当し、テストベンチのアーキテクチャ設計から検証完了までの全工程を担います。電子工学またはVLSI工学関連の学位と4〜10年の実務経験が必須です。SystemVerilogおよびUVM手法への習熟が求められ、複雑な設計におけるデバッグ能力が不可欠です。異なる地域のチームと連携し、動的な環境でマルチタスクを行う必要があります。
ミックスドシグナルIP設計の機能検証を担当し、テストベンチのアーキテクチャ設計から検証完了までの全工程を担います。電子工学またはVLSI工学関連の学位と4〜10年の実務経験が必須です。SystemVerilogおよびUVM手法への習熟が求められ、複雑な設計におけるデバッグ能力が不可欠です。異なる地域のチームと連携し、動的な環境でマルチタスクを行う必要があります。
Performs functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to mixed signal microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology.
Minimum Qualifications
Preferred Qualifications
Experienced Hire
Shift 1 (India)
India, Bangalore
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
N/A
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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