IntelはMixed Signal Design Verification Engineerを募集しています。混合信号ロジックの機能検証やアナログ動作モデリングを担当し、System Verilog、UVM、Verilogのスキルが必須です。ASIC/SoC検証における3〜4年以上の実務経験が求められます。勤務地はインドのバンガロールで、オフィスへの出社が必須となります。
Performs functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to mixed signal microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology.
Minimum Qualifications
Preferred Qualifications
Join us to shape the future of technology by driving verification excellence at Intel. Apply today and be a part of our journey to deliver world-class innovations.
Experienced Hire
Shift 1 (India)
India, Bangalore
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
N/A
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
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