IntelではMixed Signal Design Verification Engineerを募集しています。System VerilogやUVMを用いたIP検証やシミュレーションモデルの開発を担当します。Mixed Signal設計検証の経験と、EDAツールの活用スキルが必須です。ハイブリッド勤務が可能で、技術的な専門性を活かして検証プロセスを主導する重要な役割です。
As a Mixed Signal Design Verification Engineer, you will be instrumental in ensuring Intel's success in delivering innovative and high-quality mixed signal components. By leveraging your technical expertise in verification methodologies, you will validate and enhance the functionality of mixed signal IPs (example PCIE, UCIE, USB4/Type-C PHYs). Your work will directly contribute to Intel's leadership in cutting-edge technology, ensuring the performance, reliability, and efficiency of our products. This role offers a unique opportunity to collaborate with cross-functional teams and contribute to the development of industry-leading solutions.
Perform functional verification of mixed signal logic components, including analog behavioral modeling, to ensure compliance with design specifications.
Develop comprehensive IP verification plans, test benches, and environments to achieve thorough coverage of mixed signal microarchitecture specifications.
Define and execute simulation models to verify design performance, analyze power and timing, and identify and resolve design bugs.
Conduct root cause analysis and implement corrective measures to address failing tests in the pre silicon environment.
Collaborate with digital and analog architects, RTL developers, and physical design teams to refine and optimize architectural and microarchitectural features.
Lead technical reviews of test plans and validation proofs with design and architecture teams, ensuring meticulous documentation of findings and processes.
Maintain and enhance functional verification methodologies, infrastructure, and tools to align with evolving industry standards and best practices.
Qualifications
Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering or a related field.
3+ years of relevant industry experience with a Bachelor's degree, 2+ years with a Master's degree, or 0 years with a PhD.
Proficiency in mixed signal verification and hands on in IP verification using System Verilog, UVM, and Verilog.
Hands-on experience with industry-standard EDA tools, such as Synopsys VCS, Cadence Xcelium, or Mentor Questa, for simulation and verification.
Strong scripting skills in Python, Perl, or Tcl for automation and efficiency in testbench development.
Familiarity with standard protocols including JTAG, IJTAG, CRI, and APB, as well as multi-clock domain mixed signal designs.
Expertise in constraint-random test generation, root cause analysis, and debugging of complex mixed signal designs.
Experience with low-power design techniques, including UPF and clock gating, to optimize power consumption.
Knowledge of Formal Property Verification tools and version control systems such as Git or Perforce.
Strong collaboration and communication skills with the ability to thrive in a dynamic, multi-disciplinary team environment.
Join us to drive verification excellence at Intel and shape the future of technology. Apply today and be part of our journey to deliver transformative innovations.
Experienced Hire
Shift 1 (India)
India, Bangalore
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
N/A
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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