Job Details:

Job Description:

The Role and Impact
As an IP Design Verification Engineer, you will play a key role in ensuring the functionality and performance of Intel's cutting-edge intellectual property (IP) designs for system-on-chip (SoC) applications. You will be directly contributing to the next-generation LPDDR5 and DDR5 PHY verification efforts on Intel's leading process nodes. By joining our dynamic and innovative team, you will have the unique opportunity to shape the development of groundbreaking technologies that drive the future of computing.

Your work will involve collaborating with architects, RTL developers, and physical design teams to validate complex architectural and microarchitectural features. Through your expertise, you will ensure the robustness of Intel's IP designs, delivering critical contributions to the broader goals of Intel's success.

Key Responsibilities :

Own RTL validation for functional and/or DFx (design for test/debug).
Develop OVM/UVM-based test benches as a platform for RTL validation.
Define verification strategies, methodologies, and detailed test plans for effective RTL validation.
Create Bus Functional Models (BFM) to interface with the IP, monitor transactions, and verify protocol compliance.
Implement and execute test cases, assertions, and functional coverage using System Verilog, ensuring alignment with verification plans.
Set up and perform gate-level simulations (GLS) to verify asynchronous and multi-cycle paths.
Debug test failures in RTL and GLS environments, identifying root causes and implementing corrective measures.
Analyze functional and code coverage metrics to identify gaps and achieve full verification coverage.
Automate pre-silicon validation flows by creating tools or scripts, leveraging programming languages such as Tcl, Tk, Perl, or Python.
Collaborate with system and SoC teams on IP integration, ensuring smooth integration and resolving all related issues.
Maintain and enhance verification methodologies, contributing to the improvement of validation infrastructure.

Qualifications:

Minimum Qualifications :

Bachelor's or advanced degree in Electrical Engineering, Computer Engineering, or a related discipline.
6+ years of experience with a Bachelor's degree, 4+ years with a Master's degree, or 2+ years with a PhD.
Strong proficiency in System Verilog and verification methodologies such as OVM and UVM.
Expertise in DDR protocols, particularly LPDDR5 and DDR5, with experiences covering all stages of validation from specifications to coverage.
Skilled in RTL validation, logic design, DFx concepts, and IP microarchitecture debug methodologies.
Experience with industry-standard verification tools such as VCS, DVE, Verdi, or similar tools.
Familiarity with UNIX environments and fluency in shell scripting and C programming.

Preferred Qualifications :

Proven experience in IP validation across multiple full project lifecycles.
Advanced problem-solving skills with the ability to debug simulation failures and resolve formal verification challenges.
Proficiency in automating verification processes using Tcl, Tk, Perl, and Python to improve efficiency and scalability.
Strong oral and written communication skills, with the ability to work effectively with cross-functional teams and global partners.

Join us in pushing the boundaries of technology and innovation. Your contributions will help shape the future of computing at Intel. Apply today and become a part of our journey to create world-changing technologies.

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

IP設計検証エンジニア

Job Details:

Job Description:

Qualifications:

Job Type:

Shift:

Primary Location:

Additional Locations:

Business group:

Posting Statement:

Position of Trust

Work Model for this Role

Job Details:

Job Description:

Qualifications:

Job Type:

Shift:

Primary Location:

Additional Locations:

Business group:

Posting Statement:

Position of Trust

Work Model for this Role