Intelではデザイン検証インターンを募集しています。大学3〜4年生を対象とし、SystemVerilogおよびデジタル論理設計の基礎知識が必須です。週4回の出社が可能で、6ヶ月以上のインターンシップに参加できる方を求めています。UVMおよびPythonの活用能力を優遇し、グローバルプロジェクトに参加する機会を提供します。
A Design Verification (DV) Intern supports pre-silicon validation by developing testbenches, running simulations, and debugging digital ICs. They collaborate closely with RTL designers to ensure functional correctness and achieve verification closure, gaining hands-on exposure to industry-standard methodologies.
Testbench Development: Assist in developing and enhancing constrained-random verification components (e.g., sequences, monitors, scoreboards) using SystemVerilog and UVM (Universal Verification Methodology).
Simulation & Debugging: Execute regression tests, analyze waveform viewers, check coverage metrics (code/functional), and debug RTL simulation failures.
Automation & Scripting: Write and maintain automation scripts using Python, Perl, or Tcl to improve the efficiency of the verification flow.
Documentation: Maintain clear documentation of test plans, coverage results, and bug reports.
Third-year or Final-year student currently pursuing a Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science or a closely related field (Physics, Maths).
Be able to work onsite for 4 days per week.
Be able to commit to at least a 6-month internship program.
Strong verbal and written communication skills in English.
Strong foundational knowledge of digital logic design and Verilog/SystemVerilog.
Familiarity with Object-Oriented Programming (OOP) and languages like C/C++ or Python.
Basic understanding of UVM concepts, SVA (SystemVerilog Assertions), and IC design flows is highly preferred.
Soft Skills: Strong analytical and problem-solving skills, paired with a collaborative team spirit and a passion for continuous learning.
Attractive internship allowance
Training programs, opportunities to be involved in multinational projects.
Exciting extracurricular and sports programs for employees
Well-invested facilities, putting safety first.
Shuttle bus system at many places in Ho Chi Minh City, Binh Duong, Dong Nai.
High-quality cafeteria, lunch allowance.
Safe, stable and dynamic working environment.
Student / Intern
Shift 1 (Vietnam)
Vietnam, Ho_Chi_Minh_City
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
N/A
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
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