Intelは、高速IO回路およびアナログ設計を担当する経験豊富なエンジニアを募集しています。14年以上の実務経験と電気工学の修士号が必須であり、SerDes、PLL、LDOの設計専門知識が求められます。最先端のプロセスノードでアナログおよびミックスドシグナルIPを開発・最適化し、ハイブリッドワーク環境で部門横断的なチームと協力して半導体技術の革新を推進します。
The Role and Impact: As an Analog Circuit Design Engineer, you will play a pivotal role in designing and developing cutting-edge analog circuits for advanced process nodes. Your work will directly contribute to the creation of high-performance analog and mixed-signal IPs that drive Intel's innovation and leadership in the semiconductor industry. Collaborating with cross-functional teams, you will optimize circuits to meet power, performance, area, timing, and yield objectives, ensuring robust functionality and electrical capabilities. This is an opportunity to shape Intel's future technologies and make an impact in a dynamic, fast-paced environment. Key Responsibilities: - Design and develop analog circuits for advanced process nodes, focusing on analog and mixed-signal IPs. - Create floorplans, extract chip parameters, and simulate analog behavioral models to verify design intent. - Develop test plans to validate designs against circuit and block microarchitecture specifications. - Analyze test results and optimize circuits for performance, power, area, timing, and yield goals. - Collaborate with architecture and layout teams to design circuits with robust functionality and electrical capabilities. - Address design issues by collecting, tracking, and resolving performance and circuit-related problems. - Perform circuit tradeoffs to achieve the best balance between power, area, and leakage. - Ensure signal and power integrity while adhering to low-power design principles. - Provide regular updates on design progress and work collaboratively with cross-functional teams.
Minimum Qualifications: - 14+ year of experience with at least a master's degree in electrical engineering or equivalent - Expertise in designing high speed IO circuits (SerDes, LPDDR, DDR, HBM) such as transmitter, receiver, clocking, PLL, DLL, LDOs, power circuits, etc. - Expertise in analog circuit design, including LDO, TX/RX blocks, power circuits, and ADCs. - Proficiency in circuit simulation tools and methodologies. - Strong fundamentals of CMOS design, RC circuits, high speed circuit design concept, and layout principles are a must for this role - Ability to optimize circuit designs for power, performance, area, and leakage. - Hands-on experience with floor planning and static timing analysis. - Candidate needs to work with Post-Si and SoC team to debug the issue on pre/post Silicon Preferred Qualifications: - Demonstrated problem-solving skills and the ability to debug and validate analog designs. - Excellent communication skills to collaborate effectively with cross-functional teams. - Strong system-level understanding and modeling of analog circuits. - Experience in signal and power integrity optimization. - Experience with modeling and simulation of high-speed interface interconnects/channel - Experience with performing measurement, and correlating measurements to simulations - Proven ability to thrive in a fast-paced, innovative environment. Apply today and join us in shaping the future of semiconductor technology.
Experienced Hire
Shift 1 (India)
India, Bangalore
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
