アナログ回路設計エンジニア
ハードウェアエンジニア正社員シニア · 8年以上ベンガルール出社
高速SerDes PHYのアナログブロックの設計・最適化およびシリコン検証とデバッグを担当します。学士号取得者は14年以上、修士号は12年以上、博士号は8年以上の実務経験が必須です。FinFET CMOSプロセス技術の知識とCadence Virtuoso等のツール習熟度が求められます。勤務形態はオフィス出社が必須です。
高速SerDes PHYのアナログブロックの設計・最適化およびシリコン検証とデバッグを担当します。学士号取得者は14年以上、修士号は12年以上、博士号は8年以上の実務経験が必須です。FinFET CMOSプロセス技術の知識とCadence Virtuoso等のツール習熟度が求められます。勤務形態はオフィス出社が必須です。
The Role and Impact: Join Intel's cutting-edge team as an Analog Circuit Design Engineer, where you will play a pivotal role in advancing analog and mixed-signal designs for high-speed interconnect solutions. You will design and verify analog circuits in advanced process nodes, contributing directly to Intel's next-generation innovations. Collaborating with cross-functional teams, you will optimize circuits for power, performance, area, timing, and yield goals while driving impactful solutions that shape Intel's leadership in technology. This role offers the opportunity to engage with some of the most innovative teams, pushing the boundaries of analog design and fostering technical excellence. Key Responsibilities: Design and optimize highspeed SerDes PHY analog blocks for 224G/112G SerDes. Should have silicon proven hands-on design experience in couple these blocks i.e. Clock and Data Recovery circuits, Phase Interpolators, DLL, Highspeed TX drivers and RX frontends circuits. Architect lowjitter, lowpower, and highlinearity circuits meeting stringent BER and jitter specifications. Perform transistorlevel design, simulation, and optimization for PVT corners, aging, mismatch, and reliability. Work closely with SerDes architects to translate systemlevel requirements (channel loss, BER, jitter tolerance, power, latency) into circuitlevel specifications. Support linklevel modeling and behavioral abstraction of analog blocks for toplevel system simulations. Contribute to architecture tradeoffs between performance, power, area, and testability. Drive presilicon verification using Spectre/HSPICE, AMS simulations, and MATLAB/Python modeling. Define and execute postsilicon validation plans, including debug, characterization, and bringup in the lab. Analyze silicon data and correlate with simulations; propose and implement ECOs as needed. Support compliance testing with standards such as IEEE 802.3 (112G/224G) and industry interoperability requirements. Interface with digital, firmware, packaging, SI/PI, and test engineering teams. Participate in design reviews, risk assessments, and schedule planning.
Minimum Qualifications: - Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field. - 14+ years of experience with a Bachelor's degree, 12+ years with a Master's degree, or 8+ years with a Ph.D. - Expertise in analog circuit design for high-speed SerDes, transmitter, receiver, clocking, PLL, and DLL. - Strong fundamentals in CMOS design, RC circuits, high-speed circuit concepts, and signal integrity. - Proficiency in analog design tools such as Cadence Virtuoso/ADE or equivalent. - Demonstrated experience in post-silicon validation and debugging. - Knowledge of advanced FinFET CMOS process technologies. - Excellent analytical and problem-solving skills. Preferred Qualifications: - Ph.D. in Electrical Engineering, Electronics Engineering, or a related discipline. - Hands-on experience with modeling and simulation of high-speed channels and interconnects. - Familiarity with high-speed communication standards such as PCIe, Ethernet, and next-gen protocols. - Experience with Verilog-A modeling, MATLAB simulations, and automation scripting (e.g., Python, Tcl). - Demonstrated ability to mentor junior engineers and foster a collaborative team environment. - Strong communication skills, both written and verbal, to effectively influence stakeholders and drive technical decisions. Take the next step in your career by joining Intel's world-class team of innovators. Apply today and help shape the future of technology.
Experienced Hire
Shift 1 (India)
India, Bangalore
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
N/A
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.