Tenstorrent is hiring a Staff Engineer, SoC Design Verification. Candidates must have expertise in UVM and DFT/DFD verification, with proficiency in Siemens Tessent flows. You will own verification environments for AI chiplets and SoCs. This is a hybrid role open to various experienc
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Boston, Massachusetts, United States; Santa Clara, California, United States; Toronto, Ontario, Canada Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
Tenstorrent is seeking an engineer who will focus on pre-silicon verification of DFD logic in advanced AI SoCs, driving coverage of debug, test, and bring-up features critical to silicon success.
This role is hybrid, based out of Boston, MA; Toronto, Ottawa; or Santa Clara, CA.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
Deeply curious about silicon debug/test infrastructure and its verification.
Expert in UVM and verification of DFT/DFD features, scan, and on-chip trace logic.
Comfortable working with Siemens Tessent flows, iJTAG, and advanced verification automation.
Proactive, detail-oriented, and thrives in cross-functional technical discussions.
Ideally familiar with tools similar to CocoTB
What We Need
Develop and own verification environments for DFD logic across AI chiplets and SoCs.
Write, refine, and execute test scenarios for scan, MBIST, array dump, and clock-stop features.
Analyze coverage gaps, debug failures, and collaborate closely with DFT and RTL teams.
Automate flows for JTAG/scanchain testing and integrate AI productivity tools.
What You Will Learn
In-depth DFD/DFT verification using cutting-edge Tessent workflows and scripting.
Integration of pre-silicon DFD verification with silicon debug strategies.
How AI-driven automation reshapes modern DV workflows.
Exposure to security-conscious debug methodologies in advanced SoC designs.
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
