You will develop backend software for emulation systems and optimize multi-FPGA partitioning algorithms. A Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related field is required, along with a strong foundation in algorithms, data structures, and graph/hypergraph partitioning. You must have experience with C/C++ and performance-oriented development on Linux.
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Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.
Job Description
Date posted 06/07/2026
Category Engineering Hire Type Employee Job ID 17671 Remote Eligible No Date Posted 06/07/2026
Job Title: R&D Engineering, Engineer
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You are a passionate software engineer with a strong background in algorithms and system-level thinking. You enjoy solving complex problems and are driven to build scalable and efficient backend solutions for large-scale hardware systems.
What You’ll Be Doing
Develop and optimize multi-FPGA partitioning algorithms for theZeBuemulation compile flow, going beyond pure cut-size minimization
Build timing-aware partitioning solutions that incorporate critical path timing criticality into partition cost models and optimization objectives
Account for ZeBuclocking constraints—such as driver-clock-driven user clocks via multi-cycle paths—when evaluating partition quality and feasibility
Design and enhance a more robust partitioning engine that reduces sensitivity to randominitialsolutions in traditional hMetis-based flows
analytical partitioning approaches to improve initial solution quality, stability, and reproducibility
Work on constraint-aware partitioning for logic/memory resources, inter-FPGA connectivity, and timing-related partition constraints
Collaborate closely with the FPGA P&R and runtime teams tovalidatepartitioning decisions and support ZeBuplatform sign-off
Analyze partitioning bottlenecks and implement scalable, maintainable C/C++ backend components on Linux
The Impact You Will Have
Improve emulation performance by making partitioning timing-aware, not just cut-size driven
Increase partitioning robustness and reproducibility by reducing dependence on random initial solutions
Improve partition quality and compile outcomes for large SoC designs through a more stable partitioning engine
Enable successful ZeBu platform sign-off by delivering partitioning solutions validated with FPGA P&R and runtime teams
Advance state-of-the-art emulation partitioning by combining classical graph partitioning with analytical optimization techniques
What You’ll Need
Bachelor’s or master’sdegree in computer science, Electrical Engineering, or a related field
Strong foundationin algorithms, data structures, and graph/hypergraph partitioning
Experience with C/C++ and performance-oriented software development on Linux/Unix.Script languageslikepython,tclareplus
Knowledge of optimization techniques and partitioning algorithms (e.g.,hMetis, multi-way partitioning,heuristicand analytical methods)
Understanding of timing-aware optimization or willingness to developexpertisein timing-critical partitioning
Preferred: Basic exposure to clock synthesis or multi-cycle path concepts, to better reason about timing-related partition constraints
Preferred: Background in analytical approaches to partitioning or large-scale optimization (e.g., spectral, eigenvector-based, or other mathematically grounded methods)
Strong problem-solving, debugging, and experimental evaluation skills
Who You Are
Analytical and detail-oriented
Passionate about algorithm design and performance optimization
Self-motivated and able to work independently
A strong teamplayer withgood communicationskills
Eager to learn and adapt tonew technologies
The Team You'll Be Part Of
You will be part of a highly skilled R&D team working on backend software for emulation systems. The team collaborates closely with global hardware verification engineering teams to deliver high-performance solutions and continuously push the boundaries of verification technology.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
Benefits
At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
As an applicant your resume, skills, and experience are being reviewed for consideration.
Phone Screen
Once your resume has been selected a recruiter and/or hiring manager will reach out to learn more about you and share more about the role.
Interview
You will be invited to meet with the hiring team to measure your qualifications for the role. Our interviews are held either in person or via Zoom.
Offer
Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept!
Onboarding
There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation.
Welcome!
Once you’ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you’ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!
