Physical Design Engineer (Senior/Staff) in District 7
Hardware EngineerFull-timeSenior · 3–6 yearsHo Chi Minh City—
You will own physical implementation using Fusion Compiler or ICC2, from floorplanning to signoff, while acting as a technical advisor to customer teams. A degree in Electronics Engineering or equivalent and 3 to 6+ years of hands-on P&R experience are required. You must be proficient in TCL, PERL, or Python for automation. The role involves mentoring junior engineers and requires effective English communication for customer-facing collaboration.
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Physical Design Engineer (Senior/Staff) in District 7
Ho Chi Minh City, Ho Chi Minh, Vietnam
Engineering
Employee
Overview
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
Job Description
Date posted 08/03/2026
Category Engineering Hire Type Employee Job ID 18282 Date Posted 08/03/2026
Alternate Job Titles
Physical Design Engineer (Senior/Staff)
Place and Route Engineer (Senior/Staff)
SOC Physical Implementation Engineer
Backend Design Engineer (Senior/Staff)
ASIC Physical Design Engineer
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent years in physical design where routing decisions determine whether a chip tapes out clean or burns weeks in ECO. You know Fusion Compiler or ICC2 from debugging congestion hotspots and timing violations at 2am, not from training slides. P&R is equal parts science and pattern recognition, and you have developed both.
You do not wait for a perfect floorplan. You flag what will break and propose something workable before it becomes a schedule problem. When extraction results look wrong, you dig until you understand why. The best solutions often come from walking to the frontend team and asking the right question.
Mentorship matters to you. You remember staring at a million DRC violations as a junior engineer, so you take time to show someone how to read a timing report or why their power grid will not close. You script your way out of repetitive work in TCL or PERL, and you know when automation helps versus when manual is faster.
At Synopsys, you will work on real SOC designs using the tools the industry depends on. The problems are hard, the work is real, and what you build will matter.
What You'll Be Doing
Own physical implementation using Fusion Compiler or ICC2, from floorplanning through routing and signoff closure
Debug complex P&R issues including timing, congestion, IR drop, and physical verification failures across hierarchical designs
Guide customer design and CAD teams on tool usage, methodology, and design closure as a trusted technical advisor
Develop physical design flows and automation scripts in TCL, PERL, or Python to improve efficiency
Work with Synopsys BU and Sales teams to deploy tool and IP solutions that solve real customer problems
Mentor junior engineers on P&R fundamentals, debugging techniques, and tool best practices
The Impact You Will Have
Accelerate customer tapeout schedules by solving physical design bottlenecks that would otherwise cause weeks of delay
Improve Synopsys physical design methodologies through real-world deployment and customer feedback
Enable successful Fusion Compiler and ICC2 adoption across customer teams, directly influencing tool ROI
Reduce design respins by catching physical implementation problems early in the flow
Build long-term team capability by elevating junior engineer skills and reducing external support dependency
Shape EDA tool development by surfacing customer pain points that matter
Contribute to silicon products powering AI, automotive, mobile, and data center applications worldwide
What You'll Need
Bachelor's, Master's, or PhD in Electronics Engineering, Electromechanics, Telecommunications, or equivalent
3 to 6+ years hands-on Place and Route experience using Fusion Compiler or ICC2 on complex SOC or ASIC designs
Strong knowledge of P&R, extraction, static timing analysis, IR drop, and physical verification fundamentals
Proficiency in TCL, PERL, or Python scripting for automation and flow development
Solid debugging skills to trace root causes across timing, power, signal integrity, and DRC/LVS domains
Experience with signoff tools like PrimeTime, Redhawk, StarRC, or ICV is a plus
Effective English communication skills for customer-facing and cross-functional work
Who You Are
You explain complex timing paths or IR drop issues to customers in ways that clarify tradeoffs, not just symptoms
You work independently on ambiguous problems but escalate before issues become crises
You treat mentorship as part of the job and genuinely want junior engineers to succeed
You stay organized across multiple projects without letting details slip when priorities shift
You read release notes, try new features, and give real feedback instead of just complaining
You collaborate naturally with customer CAD leads, BU engineers, and Sales teams
The Team You'll Be Part Of
You will join the SOC Engineering team in Ho Chi Minh City, focused on developing and implementing advanced SOC designs using Synopsys EDA tools and IP. This team works closely with Business Units and Sales to deliver turnkey projects and customer-facing technical advisory services across the full design cycle from architecture through post-silicon validation.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
Benefits
At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
When you apply to join us, your resume, skills, and experience are first reviewed for consideration.
Phone Screen
Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have.
Interview
Next up is interviewing (in person or virtual). You’ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you’re looking for in your next role.
Offer
Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept!
Onboarding
There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation.
Welcome!
Once you’ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you’ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!
