Development of AI Accelerator LSI for Accelerating LLM Processing (Functional Verification Model, Performance Verification Model, and Logic Verification Model Construction - Sub-leader Class)

You will develop functional, performance, and logical verification models for AI accelerator LSI and lead the development of multiple blocks as a sub-leader. You must have experience in LSI front-end design and RTL design verification using Verilog, SystemVerilog, or SystemC. Fundamental knowledge of logic circuit design is required. This is a hybrid role requiring occasional on-site meetings at the Fujitsu Technology Park in Kanagawa.